| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_dp.c | 45 nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd)
50 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
69 u8 dpcd[8]; local in function:nouveau_dp_detect
76 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
80 nv_encoder->dp.link_bw = 27000 * dpcd[1];
81 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
83 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
84 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
97 nouveau_dp_probe_oui(dev, aux, dpcd);
[all...] |
| nouveau_encoder.h | 109 int nv50_mstm_detect(struct nv50_mstm *, u8 dpcd[8], int allow);
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dp_helper.h | 37 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
112 /* DPCD */
433 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
485 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
626 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
627 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
628 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
629 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
924 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ *
[all...] |
| drm_dp_mst_helper.h | 84 * @dpcd_rev: DPCD revision of device on this port. Protected by
575 * @lock: protects @mst_state, @mst_primary, @dpcd, and
605 * @dpcd: Cache of DPCD for primary port.
607 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:drm_dp_mst_topology_mgr
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_dp.c | 261 const u8 dpcd[DP_DPCD_SIZE],
268 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
269 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
330 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
351 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
353 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
354 dig_connector->dpcd);
361 dig_connector->dpcd[0] = 0;
413 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
487 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:amdgpu_atombios_dp_link_train_info
[all...] |
| amdgpu_mode.h | 473 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:amdgpu_connector_atom_dig
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_link_training.c | 158 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
189 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
198 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
259 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
274 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
309 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
|
| intel_dp.c | 169 /* update sink rates from dpcd */
177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
221 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
265 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
1378 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1939 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
2560 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2570 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2585 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3171 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thu
5324 u8 *dpcd = intel_dp->dpcd; local in function:intel_dp_detect_dpcd
[all...] |
| intel_lspcon.c | 84 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) {
186 DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n",
389 /* DPCD write for AVI IF can fail on a slow FW day, so retry */
398 DRM_ERROR("DPCD write failed at:0x%x\n", reg);
409 DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
419 DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
426 DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
580 DRM_ERROR("LSPCON DPCD read failed\n");
|
| intel_display_types.h | 1234 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:intel_dp
|
| intel_psr.c | 255 * if DPCD read fails
456 drm_dp_tps3_supported(intel_dp->dpcd))
|
| intel_ddi.c | 4230 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_dp.c | 319 const u8 dpcd[DP_DPCD_SIZE],
325 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
326 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
387 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
408 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
410 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
411 dig_connector->dpcd);
418 dig_connector->dpcd[0] = 0;
475 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
557 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:radeon_dp_link_train_info
[all...] |
| radeon_dp_mst.c | 536 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
537 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
687 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
|
| radeon_mode.h | 491 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:radeon_connector_atom_dig
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 51 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
149 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
151 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
158 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
167 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
169 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
284 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
303 * HP ZR24w corrupts the first DPCD access after entering power save
311 * We just have to do it before any DPCD access and hope that the
334 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
[all...] |
| drm_dp_mst_topology.c | 2039 * drm_dp_mst_dpcd_read() - read a series of bytes from the DPCD via sideband
2062 * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
2691 DRM_DEBUG_KMS("failed to dpcd write %d %d\n", tosend, ret);
3394 /* DPCD read should never be NACKed */
3396 DRM_ERROR("mstb %p port %d: DPCD read on addr 0x%x for %d bytes NAKed\n",
3493 DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
3522 /* get dpcd info */
3523 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
3525 DRM_DEBUG_KMS("failed to read DPCD\n");
3529 mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| display.c | 320 kfree(port->dpcd);
321 port->dpcd = NULL;
336 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
337 if (!port->dpcd) {
346 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
347 port->dpcd->data_valid = true;
348 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
|
| display.h | 63 /* DPCD start */
66 /* DPCD */
79 /* DPCD addresses */
107 /* DPCD end */
165 /* per display DPCD information */
166 struct intel_vgpu_dpcd_data *dpcd; member in struct:intel_vgpu_port
|
| handlers.c | 875 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
881 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
883 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
888 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
889 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
891 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
892 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
894 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
900 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
920 struct intel_vgpu_dpcd_data *dpcd = NULL local in function:dp_aux_ch_ctl_mmio_write
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 58 if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
59 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
167 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
245 dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
246 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
312 if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
355 const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT;
356 const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE];
413 ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
527 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd,
[all...] |
| dp.h | 26 u8 dpcd[16]; member in struct:nvkm_dp
38 /* DPCD Receiver Capabilities */
49 /* DPCD Link Configuration */
72 /* DPCD Link/Sink Status */
107 /* DPCD Sink Control */
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_disp.c | 1365 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1382 if (dpcd >= 0x12) {
1404 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1427 } else if (dpcd[0] >= 0x12) {
1428 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1432 if (!(dpcd[1] & DP_MST_CAP))
1433 dpcd[0] = 0x11;
1443 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1451 return nv50_mstm_enable(mstm, dpcd[0], 0);
1501 u8 dpcd; local in function:nv50_mstm_new
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 2401 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2406 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
4336 /* DPCD dump start address. */
4338 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4340 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
|
