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  /src/lib/libc/gen/
clock.c 1 /* $NetBSD: clock.c,v 1.10 2009/01/11 02:46:27 christos Exp $ */
35 static char sccsid[] = "@(#)clock.c 8.1 (Berkeley) 6/4/93";
37 __RCSID("$NetBSD: clock.c,v 1.10 2009/01/11 02:46:27 christos Exp $");
50 * interrupt based on when clock ticks happen. getrusage apportions the
59 clock(void) function in typeref:typename:clock_t
  /src/sys/arch/hpcmips/hpcmips/
clock.c 1 /* $NetBSD: clock.c,v 1.22 2011/03/16 14:43:36 tsutsui Exp $ */
65 * from: Utah Hdr: clock.c 1.18 91/01/21
67 * @(#)clock.c 8.1 (Berkeley) 6/10/93
71 __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.22 2011/03/16 14:43:36 tsutsui Exp $");
83 * Register CPU(VR41XX or TX39XX) dependent clock routine to system.
86 platform_clock_attach(device_t dev, struct platform_clock *clock)
91 clock->self = dev;
92 platform.clock = clock;
105 struct platform_clock *clock = platform.clock local in function:cpu_initclocks
    [all...]
  /src/sys/arch/arc/include/
platform.h 43 int clock; /* CPU clock [MHz] */ member in struct:platform
  /src/sys/arch/hpcmips/include/
sysconf.h 63 * clock -
71 struct platform_clock *clock; member in struct:platform
  /src/sys/arch/playstation2/playstation2/
interrupt.h 50 struct evcnt clock, sbus, dmac; member in struct:_playstation2_evcnt
  /src/tests/dev/clock_subr/
t_clock_subr.c 46 { .time = (ti), .clock = { .dt_year = (ye), .dt_mon = (mo), .dt_day = (da), \
51 struct clock_ymdhms clock; member in struct:clock_test
266 secs = clock_ymdhms_to_secs(__UNCONST(&clock_tests[i].clock));
284 ATF_CHECK_EQ_MSG(ymdhms.dt_##f, clock_tests[i].clock.dt_##f, \
286 (intmax_t)clock_tests[i].clock.dt_##f, \
  /src/sys/arch/sparc64/dev/
pcfiic_ebus.c 93 u_int8_t clock = PCF8584_CLK_12 | PCF8584_SCL_90; local in function:pcfiic_ebus_attach
101 /* E450 and E250 have a different clock */
104 clock = PCF8584_CLK_12 | PCF8584_SCL_45;
112 * it a non-standard clock.
114 int clk = prom_getpropint(findroot(), "clock-frequency", 0);
117 clock = PCF8584_CLK_3 | PCF8584_SCL_90;
119 clock = PCF8584_CLK_4_43 | PCF8584_SCL_90;
165 pcfiic_attach(sc, (i2c_addr_t)(addr >> 1), clock, swapregs);
  /src/sys/dev/usb/
aubtfwlreg.h 20 uint8_t clock; member in struct:ar3k_version
aubtfwl.c 279 int clock = 0; local in function:aubtfwl_attach_hook
305 switch (ver.clock) {
307 clock = 19;
310 clock = 26;
313 clock = 40;
318 ver.rom, clock);
  /src/usr.sbin/btattach/
init_bcm43xx.c 94 uint8_t rate[6], clock; local in function:init_bcm43xx
145 clock = BCM43XX_CLK_48;
147 clock = BCM43XX_CLK_24;
149 uart_send_cmd(fd, HCI_CMD_BCM43XX_SET_CLOCK, &clock, sizeof(clock));
  /src/sys/arch/hpcmips/dev/
mq200subr.c 72 { 640, 480, 25175, /* width, height, dot clock */
82 { 800, 600, 40000, /* width, height, dot clock */
90 { 1024, 768, 65000, /* width, height, dot clock */
150 mq200_set_pll(struct mq200_softc *sc, int pll, int clock)
175 if (clock != 0 && clock != -1) {
177 if (mq200_pllparam(clock, &param) != 0) {
178 printf("mq200: invalid clock rate: %s %d.%03dMHz\n",
179 mq200_clknames[pll], clock/1000, clock%1000)
219 const struct mq200_clock_setting *clock; local in function:mq200_setup
    [all...]
mq200priv.h 33 u_int16_t width, height, clock; member in struct:mq200_crt_param
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
exynos5410.dtsi 14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 label in label:soc
    [all...]
exynos4210.dtsi 50 clocks = <&clock CLK_ARM_CLK>;
51 clock-names = "cpu";
52 clock-latency = <160000>;
69 clocks = <&clock CLK_ARM_CLK>;
70 clock-names = "cpu";
71 clock-latency = <160000>;
125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
126 clock-names = "fin_pll", "mct";
139 clocks = <&clock CLK_WDT>
143 clock: clock-controller@10030000 { label
    [all...]
exynos4412.dtsi 59 clocks = <&clock CLK_ARM_CLK>;
60 clock-names = "cpu";
69 clocks = <&clock CLK_ARM_CLK>;
70 clock-names = "cpu";
79 clocks = <&clock CLK_ARM_CLK>;
80 clock-names = "cpu";
89 clocks = <&clock CLK_ARM_CLK>;
90 clock-names = "cpu";
103 clock-latency-ns = <200000>;
108 clock-latency-ns = <200000>
249 clock: clock-controller@10030000 { label
    [all...]
hi3620.dtsi 11 #include <dt-bindings/clock/hi3620-clock.h>
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
102 clock: clock@0 { label in label:sysctrl
103 compatible = "hisilicon,hi3620-clock";
105 #clock-cells = <1>
    [all...]
hisi-x5hd2.dtsi 7 #include <dt-bindings/clock/hix5hd2-clock.h>
44 clocks = <&clock HIX5HD2_FIXED_24M>;
58 clocks = <&clock HIX5HD2_FIXED_24M>;
67 clocks = <&clock HIX5HD2_FIXED_24M>;
76 clocks = <&clock HIX5HD2_FIXED_24M>;
85 clocks = <&clock HIX5HD2_FIXED_24M>;
93 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
94 clock-names = "uartclk", "apb_pclk"
412 clock: clock@0 { label
    [all...]
  /src/sys/arch/ews4800mips/stand/common/
console.h 102 int clock; member in struct:zs
  /src/sys/dev/ic/
pl181.c 341 uint32_t clock; local in function:plmmc_bus_clock
343 clock = MMCI_CLOCK_PWRSAVE;
347 clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);
348 clock |= MMCI_CLOCK_ENABLE;
350 MMCI_WRITE(sc, MMCI_CLOCK_REG, clock);
  /src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/
tsan_defs.h 58 ClockElem clock[kClockCount]; member in union:__tsan::ClockBlock::__anon41da20c0010a
tsan_sync.h 67 // The clock is placed last, so that it is situated on a different cache line
69 SyncClock clock; member in struct:__tsan::SyncVar
  /src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/unit/
tsan_clock_test.cc 23 TEST(Clock, VectorBasic) {
39 TEST(Clock, ChunkedBasic) {
60 TEST(Clock, Iter) {
81 TEST(Clock, AcquireRelease) {
97 TEST(Clock, RepeatedAcquire) {
112 TEST(Clock, ManyThreads) {
138 TEST(Clock, DifferentSizes) {
177 TEST(Clock, Growth) {
242 TEST(Clock, Growth2) {
243 // Test clock growth for every pair of sizes
282 u64 clock[kThreads]; member in struct:__tsan::SimpleSyncClock
311 u64 clock[kThreads]; member in struct:__tsan::SimpleThreadClock
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios_crtc.c 320 u32 adjusted_clock = mode->clock;
322 u32 dp_clock = mode->clock;
323 u32 clock = mode->clock; local in function:amdgpu_atombios_crtc_adjust_pll
325 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
354 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
356 adjusted_clock = mode->clock * 2;
370 clock = (clock * 5) / 4;
373 clock = (clock * 3) / 2
831 u32 clock = mode->clock; local in function:amdgpu_atombios_crtc_set_pll
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
nouveau_dispnv04_hw.c 240 uint32_t clock; local in function:nouveau_hw_get_clock
243 0x4c, &clock);
244 return clock / 1000;
282 /* set lowest clock within static limits */
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_mcp77.c 61 u32 clock = 0; local in function:read_pll
78 clock = ref * N1 / M1;
79 clock = clock / post_div;
82 return clock;
98 return 100000; /* PCIE reference clock */
165 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
171 u32 clock, int *N, int *M, int *P)
186 return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
215 u32 out = 0, clock = 0 local in function:mcp77_clk_calc
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