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  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
vc4_opt_coalesce_ff_writes.c 45 qir_for_each_inst_inorder(inst, c) {
46 for (int i = 0; i < qir_get_nsrc(inst); i++) {
47 if (inst->src[i].file == QFILE_TEMP) {
48 uint32_t temp = inst->src[i].index;
70 struct qinst *inst = c->defs[temp]; local
71 if (!inst)
78 if (qir_is_tex(mov_inst) && qir_has_uniform_read(inst))
81 if (qir_depends_on_flags(inst) || inst->sf)
84 if (qir_has_side_effects(c, inst) ||
    [all...]
vc4_cl_dump.c 51 struct v3d_group *inst = v3d_spec_find_instruction(spec, p); local
55 if (inst == NULL) {
61 length = v3d_group_get_length(inst);
64 offset, hw_offset, header, v3d_group_get_name(inst));
66 v3d_print_group(clif, inst, offset, p);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
vc4_opt_coalesce_ff_writes.c 45 qir_for_each_inst_inorder(inst, c) {
46 for (int i = 0; i < qir_get_nsrc(inst); i++) {
47 if (inst->src[i].file == QFILE_TEMP) {
48 uint32_t temp = inst->src[i].index;
70 struct qinst *inst = c->defs[temp]; local
71 if (!inst)
78 if (qir_is_tex(mov_inst) && qir_has_uniform_read(inst))
81 if (qir_depends_on_flags(inst) || inst->sf)
84 if (qir_has_side_effects(c, inst) ||
    [all...]
vc4_cl_dump.c 51 struct v3d_group *inst = v3d_spec_find_instruction(spec, p); local
55 if (inst == NULL) {
61 length = v3d_group_get_length(inst);
64 offset, hw_offset, header, v3d_group_get_name(inst));
66 v3d_print_group(clif, inst, offset, p);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
radeon_pair_dead_sources.c 46 struct rc_instruction * inst,
54 inst->U.P.RGB.Src[sub->Arg[i].Source].Used = 1;
58 inst->U.P.Alpha.Src[sub->Arg[i].Source].Used = 1;
69 struct rc_instruction * inst; local
70 for (inst = c->Program.Instructions.Next;
71 inst != &c->Program.Instructions;
72 inst = inst->Next) {
74 if (inst->Type == RC_INSTRUCTION_NORMAL)
79 inst->U.P.RGB.Src[i].Used = 0
    [all...]
radeon_rename_regs.c 50 struct rc_instruction * inst; local
56 for(inst = c->Program.Instructions.Next;
57 inst != &c->Program.Instructions;
58 inst = inst->Next) {
59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
75 if (var->Inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_vec4_vs_visitor.cpp 55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); local
56 inst->urb_write_flags = complete ?
59 return inst;
78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0); local
79 if (inst && key->clamp_vertex_color)
80 inst->saturate = true;
brw_dead_control_flow.cpp 51 backend_instruction *const inst = block->start(); local
57 if (inst->opcode == BRW_OPCODE_ENDIF &&
64 } else if (inst->opcode == BRW_OPCODE_ENDIF &&
68 backend_instruction *const endif_inst = inst;
101 } else if (inst->opcode == BRW_OPCODE_ELSE &&
105 backend_instruction *const else_inst = inst;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
radeon_pair_dead_sources.c 46 struct rc_instruction * inst,
54 inst->U.P.RGB.Src[sub->Arg[i].Source].Used = 1;
58 inst->U.P.Alpha.Src[sub->Arg[i].Source].Used = 1;
69 struct rc_instruction * inst; local
70 for (inst = c->Program.Instructions.Next;
71 inst != &c->Program.Instructions;
72 inst = inst->Next) {
74 if (inst->Type == RC_INSTRUCTION_NORMAL)
79 inst->U.P.RGB.Src[i].Used = 0
    [all...]
radeon_rename_regs.c 50 struct rc_instruction * inst; local
56 for(inst = c->Program.Instructions.Next;
57 inst != &c->Program.Instructions;
58 inst = inst->Next) {
59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
75 if (var->Inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
  /xsrc/external/mit/MesaLib/dist/src/broadcom/clif/
v3dx_dump.c 64 struct v3d_group *inst = v3d_spec_find_instruction(clif->spec, cl); local
65 if (!inst) {
70 *size = v3d_group_get_length(inst);
73 char *name = clif_name(v3d_group_get_name(inst));
76 v3d_print_group(clif, inst, 0, cl);
  /xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/tests/
qpu_disasm.c 34 uint64_t inst; member in struct:__anon630
130 (long long)tests[i].inst,
134 tests[i].inst);
146 if (!v3d_qpu_instr_unpack(&devinfo, tests[i].inst, &instr)) {
178 if (repack != tests[i].inst) {
  /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
lower_vertex_id.cpp 113 ir_instruction *const inst = local
117 main_sig->body.push_head(inst);
  /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
lp_bld_tgsi_action.h 92 const struct tgsi_full_instruction * inst; member in struct:lp_build_emit_data
  /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/
tgsi_vpos.c 61 struct tgsi_full_instruction inst; local
67 inst = tgsi_default_full_instruction();
68 inst.Instruction.Opcode = TGSI_OPCODE_MOV;
69 inst.Instruction.NumDstRegs = 1;
70 tgsi_transform_dst_reg(&inst.Dst[0], TGSI_FILE_OUTPUT,
72 inst.Instruction.NumSrcRegs = 1;
73 tgsi_transform_src_reg(&inst.Src[0], TGSI_FILE_IMMEDIATE,
76 ctx->emit_instruction(ctx, &inst);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/tests/
radeon_compiler_optimize_tests.c 56 struct rc_instruction *inst; local
67 for(inst = c.Program.Instructions.Next;
68 inst != &c.Program.Instructions;
69 inst = inst->Next, inst_count++) {
70 inst_list[inst_count] = inst;
radeon_compiler_regalloc_tests.c 53 struct rc_instruction *inst; local
67 for(inst = c->Program.Instructions.Next;
68 inst != &c->Program.Instructions;
69 inst = inst->Next) {
70 if (inst->Type == RC_INSTRUCTION_NORMAL &&
71 inst->U.I.Opcode != RC_OPCODE_BEGIN_TEX) {
72 if (GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 0)
  /xsrc/external/mit/MesaLib.old/dist/src/broadcom/clif/
v3dx_dump.c 64 struct v3d_group *inst = v3d_spec_find_instruction(clif->spec, cl); local
65 if (!inst) {
70 *size = v3d_group_get_length(inst);
73 char *name = clif_name(v3d_group_get_name(inst));
76 v3d_print_group(clif, inst, 0, cl);
  /xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/tests/
qpu_disasm.c 33 uint64_t inst; member in struct:__anon3303
129 (long long)tests[i].inst,
133 tests[i].inst);
144 if (!v3d_qpu_instr_unpack(&devinfo, tests[i].inst, &instr)) {
175 if (repack != tests[i].inst) {
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
lower_vertex_id.cpp 113 ir_instruction *const inst = local
117 main_sig->body.push_head(inst);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
lp_bld_tgsi_action.h 92 const struct tgsi_full_instruction * inst; member in struct:lp_build_emit_data
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/tests/
radeon_compiler_optimize_tests.c 56 struct rc_instruction *inst; local
67 for(inst = c.Program.Instructions.Next;
68 inst != &c.Program.Instructions;
69 inst = inst->Next, inst_count++) {
70 inst_list[inst_count] = inst;
radeon_compiler_regalloc_tests.c 53 struct rc_instruction *inst; local
67 for(inst = c->Program.Instructions.Next;
68 inst != &c->Program.Instructions;
69 inst = inst->Next) {
70 if (inst->Type == RC_INSTRUCTION_NORMAL &&
71 inst->U.I.Opcode != RC_OPCODE_BEGIN_TEX) {
72 if (GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 0)
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_dead_control_flow.cpp 49 backend_instruction *const inst = block->start(); local
55 if (inst->opcode == BRW_OPCODE_ENDIF &&
62 } else if (inst->opcode == BRW_OPCODE_ENDIF &&
66 backend_instruction *const endif_inst = inst;
99 } else if (inst->opcode == BRW_OPCODE_ELSE &&
103 backend_instruction *const else_inst = inst;
brw_vec4_vs_visitor.cpp 55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); local
56 inst->urb_write_flags = complete ?
59 return inst;
78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0); local
79 if (inst && key->clamp_vertex_color)
80 inst->saturate = true;

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1 2 3 4 5 6 7 8 91011