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  /src/sys/arch/arm/at91/
at91pmc.c 55 uint64_t mclk, pllaclk, pllbclk, pclk, mstclk; local
93 pclk = SLOW_CLOCK;
97 pclk = mclk;
100 pclk = pllaclk;
103 pclk = pllbclk;
106 pclk >>= (reg & PMC_MCKR_PRES) >> PMC_MCKR_PRES_SHIFT;
107 mstclk = pclk / (((reg & PMC_MCKR_MDIV) >> PMC_MCKR_MDIV_SHIFT) + 1);
111 clocks->cpu = pclk;
  /src/sys/arch/evbarm/stand/board/
smdk2800_io_init.c 58 unsigned int pclk; local
95 pclk = hclk / 2;
97 pclk = hclk;
100 if((pclk/F_1MHZ) < 1)
103 tmdat = (pclk/F_1MHZ)<<16;
sscom.c 104 long pclk = get_com_freq(); local
108 x = divrnd(pclk / 16, speed);
111 err = divrnd(((quad_t)pclk) * 1000 / 16, speed * x) - 1000;
  /src/sys/arch/arm/s3c2xx0/
s3c2410_spi.c 165 int pclk = s3c2xx0_softc->sc_pclk; local
172 prescaler = pclk / 2 / bps - 1;
s3c2440_spi.c 207 int pclk = s3c2xx0_softc->sc_pclk; local
214 prescaler = pclk / 2 / bps - 1;
319 int pclk = s3c2xx0_softc->sc_pclk; local
323 prescaler = pclk / 2 / bps - 1;
s3c24x0_clk.c 54 #define TIMER_FREQUENCY(pclk) ((pclk)/16) /* divider=1/16 */
63 #define counter_to_usec(c,pclk) \
64 (((c)*timer4_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000))
220 int pclk = s3c2xx0_softc->sc_pclk; local
228 #define time_constant(hz) (TIMER_FREQUENCY(pclk) /(hz)/ prescaler)
249 timer4_reload_value = (TIMER_FREQUENCY(pclk) / hz / prescaler) - 1;
250 timer4_mseccount = TIMER_FREQUENCY(pclk)/timer4_prescaler/1000 ;
255 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n",
256 hz, stathz, pclk, prescaler, tc)
    [all...]
s3c2800_clk.c 58 #define TIMER_FREQUENCY(pclk) ((pclk)/32) /* divider=1/32 */
67 #define counter_to_usec(c,pclk) \
68 (((c)*timer0_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000))
224 int pclk = s3c2xx0_softc->sc_pclk; local
234 tc = TIMER_FREQUENCY(pclk) /(hz)/ prescaler; \
249 timer0_mseccount = TIMER_FREQUENCY(pclk)/timer0_prescaler/1000 ;
251 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n",
252 hz, stathz, pclk, prescaler, tc);
285 s3c2800_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer0_prescaler
    [all...]
s3c2440_i2s.c 189 int pclk = s3c2xx0_softc->sc_pclk; /* Peripherical Clock in Hz*/ local
197 codecClockPrescaler = pclk/codecClock;
201 DPRINTF(("Actual CODEC Clock: %d Hz\n", pclk/(codecClockPrescaler+1)));
203 (pclk/(codecClockPrescaler+1))/sc->sc_master_clock));
s3c2440_sdi.c 218 saa.saa_clkmax = s3c2xx0_softc->sc_pclk / 1; /* PCLK/1 or PCLK/2 depending on how the spec is read */
324 int pclk = s3c2xx0_softc->sc_pclk/1000; /*Peripheral bus clock in KHz*/ local
327 pclk = (pclk / 1000) * 1000;
339 if ( pclk / div <= freq) {
340 DPRINTF(("Using divisor %d: %d/%d = %d\n", div, pclk,
341 div, pclk/div));
  /src/sys/arch/arm/ep93xx/
epsoc.c 79 uint64_t fclk, pclk, hclk; local
139 pclk = hclk >> pclkdiv;
146 printf("%s: fclk %lld.%02lld MHz hclk %lld.%02lld MHz pclk %lld.%02lld MHz\n",
150 pclk / 1000000, (pclk % 1000000 + 5000) / 10000);
154 sc->sc_pclk = pclk;
  /src/sys/arch/arm/marvell/
orion.c 184 uint32_t pclk; member in struct:__anon1098
235 mvPclk = sysclktbl[i].pclk;
  /src/sys/arch/mips/ingenic/
apbus.c 129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv; local
152 pclk = mclk / pdiv;
157 aprint_debug_dev(self, "pclk %d kHz\n", pclk);
251 aa.aa_pclk = pclk;
  /src/sys/arch/evbarm/smdk2xx0/
smdk2800_machdep.c 820 int pclk; local
829 s3c2800_clock_freq2(ioreg_vaddr(S3C2800_CLKMAN_BASE), NULL, NULL, &pclk); local
834 pclk, comcnmode))
839 pclk, comcnmode))
876 int pclk; local
885 NULL, NULL, &pclk); local
888 unit, kgdb_rate, pclk, kgdb_sscom_mode);
smdk2410_machdep.c 896 int pclk; local
903 s3c24x0_clock_freq2(CLKMAN_VBASE, NULL, NULL, &pclk);
908 pclk, comcnmode))
913 pclk, comcnmode))
950 int pclk; local
958 s3c24x0_clock_freq2(CLKMAN_VBASE, NULL, NULL, &pclk);
961 unit, kgdb_rate, pclk, kgdb_sscom_mode);
  /src/sys/dev/ic/
cdnsiic.c 99 u_int pclk; local
105 * SCL = PCLK / SCLK Divisor
108 pclk = clk_get_rate(sc->sc_pclk);
113 divb = howmany(pclk, 22 * sc->sc_bus_freq * (diva + 1)) - 1;
117 calc_bus_freq = pclk / (22 * (diva + 1) * (divb + 1));
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dsi.h 120 u32 pclk; member in struct:intel_dsi
vlv_dsi_pll.c 48 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
56 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
129 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
265 u32 dsi_clock, pclk; local
318 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
320 return pclk;
326 u32 pclk; local
339 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
341 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
    [all...]
vlv_dsi.c 1198 u32 pclk; local
1205 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1207 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1210 if (pclk) {
1211 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1212 pipe_config->port_clock = pclk;
1909 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
1910 intel_dsi->pclk, current_mode->clock);
1911 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1913 DRM_DEBUG_KMS("Using GOP pclk\n")
    [all...]
  /src/sys/arch/news68k/dev/
zs.c 83 static const u_int pclk[NPCLK] = { variable
234 cs->cs_brg_clk = pclk[clk] / 16;
579 cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
  /src/sys/arch/evbarm/mini2440/
mini2440_machdep.c 927 int pclk; local
934 s3c24x0_clock_freq2(CLKMAN_VBASE, NULL, NULL, &pclk);
939 pclk, comcnmode))
944 pclk, comcnmode))
981 int pclk; local
989 s3c24x0_clock_freq2(CLKMAN_VBASE, NULL, NULL, &pclk);
992 unit, kgdb_rate, pclk, kgdb_sscom_mode);
  /src/sys/arch/evbarm/stand/boot2440/
main.c 81 int *pclk);
82 static void uart_init(uint32_t pclk);
83 static void time_init(uint32_t pclk);
101 int pclk; variable
146 s3c24x0_clock_freq2(S3C2440_CLKMAN_BASE, &fclk, &hclk, &pclk);
148 uart_init(pclk);
149 time_init(pclk);
278 uart_init(uint32_t pclk)
280 /* Setup UART0 clocking: Use PCLK */
282 (pclk/(UART_BAUDRATE*16)) - 1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rs690.c 284 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; local
327 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
335 pclk.full = dfixed_div(b, a);
343 consumption_time.full = dfixed_div(pclk, b);
345 consumption_time.full = pclk.full;
354 * pclk = pixel clock period(ns)
357 line_time.full = dfixed_mul(a, pclk);
radeon_rv515.c 967 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; local
1007 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
1015 pclk.full = dfixed_div(b, a);
1023 consumption_time.full = dfixed_div(pclk, b);
1025 consumption_time.full = pclk.full;
1034 * pclk = pixel clock period(ns)
1037 line_time.full = dfixed_mul(a, pclk);
  /src/sys/arch/arm/rockchip/
rk3399_cru.c 1123 struct rk_cru_clk *clk, *pclk; local
1150 pclk = rk_cru_clock_find(sc, param->parent);
1151 KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent);
1152 error = clk_set_parent(&clk->base, &pclk->base);
rk_spi.c 203 struct clk *sclk, *pclk; local
216 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL
217 || clk_enable(pclk) != 0) {
218 aprint_error(": couldn't enable pclk\n");

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