| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| gt215.h | 10 u32 pll; member in struct:gt215_clk_info
|
| nouveau_nvkm_subdev_clk_nv40.c | 31 #include "pll.h"
34 #include <subdev/bios/pll.h>
133 struct nvbios_pll pll; local
136 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
140 if (khz < pll.vco1.max_freq)
141 pll.vco2.max_freq = 0;
143 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
173 /* use the second pll for shader/rop clock, if it differs from core */
|
| nouveau_nvkm_subdev_clk_gk20a.c | 70 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
76 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
77 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
78 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
82 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
87 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
88 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
89 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
94 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
99 rate = clk->parent_rate * pll->n
220 struct gk20a_pll pll; local
470 struct gk20a_pll pll; local
555 struct gk20a_pll pll; local
[all...] |
| nouveau_nvkm_subdev_clk_mcp77.c | 31 #include "pll.h"
34 #include <subdev/bios/pll.h>
174 struct nvbios_pll pll; local
177 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
181 pll.vco2.max_freq = 0;
182 pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href);
183 if (!pll.refclk)
186 return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
219 /* cclk: find suitable source, disable PLL if we can */
|
| nouveau_nvkm_subdev_clk_nv50.c | 30 #include "pll.h"
34 #include <subdev/bios/pll.h>
74 nvkm_error(subdev, "ref: bad pll %06x\n", base);
102 nvkm_error(subdev, "ref: bad pll %06x\n", base);
152 nvkm_error(subdev, "bad pll %06x\n", base);
333 struct nvbios_pll pll; local
336 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
340 pll.vco2.max_freq = 0;
341 pll.refclk = read_pll_ref(clk, reg);
342 if (!pll.refclk
[all...] |
| gk20a.h | 121 struct gk20a_pll pll; member in struct:gk20a_clk
145 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
147 return DIV_ROUND_UP(pll->m * clk->params->min_vco,
|
| /src/sys/arch/arm/nxp/ |
| imx_ccm_pll.c | 48 struct imx_ccm_pll *pll = &clk->u.pll; local
53 if ((pll->flags & IMX_PLL_ENET) != 0)
58 val = CCM_READ(sc, clk->regidx, pll->reg);
63 CCM_WRITE(sc, clk->regidx, pll->reg, val);
72 struct imx_ccm_pll *pll= &clk->u.pll; local
86 if ((pll->flags & IMX_PLL_ENET) != 0) {
87 /* For ENET PLL, div_mask contains the fixed output rate */
88 return pll->div_mask
109 struct imx_ccm_pll *pll = &clk->u.pll; local
[all...] |
| imx6_ccm.c | 161 struct imx6_clk_pll *pll = &iclk->clk.pll; local
164 KASSERT((pll->type == IMX6_CLK_PLL_GENERIC) ||
165 (pll->type == IMX6_CLK_PLL_USB));
167 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg);
168 uint32_t div = __SHIFTOUT(v, pll->mask);
177 struct imx6_clk_pll *pll = &iclk->clk.pll; local
180 KASSERT(pll->type == IMX6_CLK_PLL_SYS);
182 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg)
195 struct imx6_clk_pll *pll = &iclk->clk.pll; local
216 struct imx6_clk_pll *pll = &iclk->clk.pll; local
242 struct imx6_clk_pll *pll = &iclk->clk.pll; local
538 struct imx6_clk_pll *pll = &iclk->clk.pll; local
[all...] |
| imx6_ccmvar.h | 154 struct imx6_clk_pll pll; member in union:imx6_clk::__anon1105
200 .pll = { \
|
| imx_ccm.h | 170 .u.pll.parent = (_parent), \
171 .u.pll.reg = (_reg), \
172 .u.pll.div_mask = (_div_mask), \
173 .u.pll.flags = (_flags), \
298 struct imx_ccm_pll pll; member in union:imx_ccm_clk::__anon1109
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk_pll.c | 43 struct meson_clk_pll *pll = &clk->u.pll; local
62 val = CLK_READ(sc, pll->n.reg);
63 n = __SHIFTOUT(val, pll->n.mask);
65 val = CLK_READ(sc, pll->m.reg);
66 m = __SHIFTOUT(val, pll->m.mask);
68 if (pll->frac.mask) {
69 val = CLK_READ(sc, pll->frac.reg);
70 frac = __SHIFTOUT(val, pll->frac.mask);
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1)
102 struct meson_clk_pll *pll = &clk->u.pll; local
177 struct meson_clk_pll *pll = &clk->u.pll; local
[all...] |
| meson_clk.h | 229 * PLL clocks
259 struct meson_clk_pll *pll);
267 .u.pll.parent = (_parent), \
268 .u.pll.enable = _enable, \
269 .u.pll.m = _m, \
270 .u.pll.n = _n, \
271 .u.pll.frac = _frac, \
272 .u.pll.l = _l, \
273 .u.pll.reset = _reset, \
274 .u.pll.flags = (_flags),
341 struct meson_clk_pll pll; member in union:meson_clk_clk::__anon993
[all...] |
| /src/sys/dev/i2c/ |
| tvpll.c | 47 const struct tvpll_data * pll; member in struct:tvpll
63 tvpll->pll = p;
65 if (tvpll->pll->initdata) {
68 &tvpll->pll->initdata[1], tvpll->pll->initdata[0],
73 device_printf(parent, "tvpll: %s\n", tvpll->pll->name);
88 const struct tvpll_data *pll; local
92 pll = tvpll->pll;
95 (p->frequency < pll->min || p->frequency > pll->max)
[all...] |
| /src/sys/arch/mips/atheros/ |
| ar7100.c | 152 const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); local
156 ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1);
159 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1);
162 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1);
165 cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2);
|
| ar9344.c | 124 uint32_t pll; local
137 * Let's figure out the CPU PLL frequency.
139 pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG);
140 out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV);
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);
142 nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT);
143 //nfrac = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NFRAC);
148 * Now figure out the DDR PLL frequency.
150 pll = GETPLLREG(ARCHIP_PLL_DDR_PLL_CONFIG);
151 out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramnv40.c | 34 #include <subdev/bios/pll.h>
35 #include <subdev/clk/pll.h>
44 struct nvbios_pll pll; local
48 ret = nvbios_pll_parse(bios, 0x04, &pll);
50 nvkm_error(subdev, "mclk pll data not found\n");
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
59 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
127 /* change the PLL of each memory partition */
|
| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 82 struct tegra_pll_clk pll; member in union:tegra_clk::__anon1099
|
| /src/sys/arch/arm/samsung/ |
| exynos_clock.h | 78 struct exynos_pll_clk pll; member in union:exynos_clk::__anon1147
|
| /src/sys/arch/amigappc/amigappc/ |
| machdep.c | 254 static const unsigned char pll[] = { local
267 * HID1 holds the PLL configuration
332 /* compute cpuclock based on PLL configuration */
333 cpuclock = busclock * pll[hid1>>28 & 0xf] / 10;
|
| /src/sys/arch/arm/rockchip/ |
| rk3399_pmucru.c | 164 struct rk_cru_pll *pll = &clk->u.pll; local
179 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
180 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
181 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
182 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
207 struct rk_cru_pll *pll = &clk->u.pll; local
214 if (pll->rates == NULL || rate == 0)
217 for (int i = 0; i < pll->nrates; i++
[all...] |
| rk_cru_pll.c | 90 struct rk_cru_pll *pll = &clk->u.pll; local
105 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
106 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
107 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
108 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
110 if ((pll->flags & RK_PLL_RK3288) != 0) {
122 } else if ((pll->flags & RK_PLL_RK3588) != 0) {
160 struct rk_cru_pll *pll = &clk->u.pll; local
277 struct rk_cru_pll *pll = &clk->u.pll; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_crtc.c | 260 * again can cause display problems if the pll is already
273 /* one other crtc is using this pll don't turn
363 /* adjust pll for deep color modes */
833 struct amdgpu_pll *pll; local
843 pll = &adev->clock.ppll[0];
846 pll = &adev->clock.ppll[1];
851 pll = &adev->clock.ppll[2];
855 /* update pll params */
856 pll->flags = amdgpu_crtc->pll_flags;
857 pll->reference_div = amdgpu_crtc->pll_reference_div
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 33 #include <subdev/bios/pll.h>
132 * PLL getting
258 * beyond the pll limits. for some reason this causes the chip to
259 * lock up when reading the dac palette regs, so set a valid pll here
269 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; local
271 if (nvbios_pll_parse(bios, pll, &pll_lim))
273 nouveau_hw_get_pllvals(dev, pll, &pv);
862 /* NB: no attempt is made to restore the bad pll later on */
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 36 #include <subdev/bios/pll.h>
37 #include <subdev/clk/pll.h>
138 * stage pll
155 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; local
159 if (oldpll == pll)
183 nvkm_wr32(device, reg, pll);
194 if (ss) /* single stage pll mode */
|
| /src/sys/arch/x86/include/ |
| powernow.h | 135 unsigned int pll; member in struct:powernow_cpu_state
152 uint8_t pll; member in struct:powernow_pst_s
|
