| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| common_baco.h | 40 uint32_t reg_offset; member in struct:baco_cmd_entry
52 uint32_t reg_offset; member in struct:soc15_baco_cmd_entry
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| soc15.h | 51 uint32_t reg_offset; member in struct:soc15_reg_entry
61 uint32_t reg_offset; member in struct:soc15_allowed_register_entry
70 uint32_t reg_offset; member in struct:soc15_ras_field_entry
79 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
|
| amdgpu_jpeg_v1_0.c | 41 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
48 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
50 ring->ring[(*ptr)++] = reg_offset;
60 uint32_t reg, reg_offset, val, mask, i; local in function:jpeg_v1_0_decode_ring_set_patch_ring
64 reg_offset = (reg << 2);
66 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val)
350 uint32_t reg_offset = (reg << 2); local in function:jpeg_v1_0_decode_ring_emit_reg_wait
394 uint32_t reg_offset = (reg << 2); local in function:jpeg_v1_0_decode_ring_emit_wreg
[all...] |
| mmsch_v1_0.h | 65 uint32_t reg_offset : 28; member in struct:mmsch_v1_0_cmd_direct_reg_header
70 uint32_t reg_offset : 20; member in struct:mmsch_v1_0_cmd_indirect_reg_header
103 uint32_t reg_offset,
106 direct_wt->cmd_header.reg_offset = reg_offset;
113 uint32_t reg_offset,
116 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
125 uint32_t reg_offset,
128 direct_poll->cmd_header.reg_offset = reg_offset
[all...] |
| amdgpu_jpeg_v2_0.c | 605 uint32_t reg_offset = (reg << 2); local in function:jpeg_v2_0_dec_ring_emit_reg_wait
617 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
620 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
622 amdgpu_ring_write(ring, reg_offset);
646 uint32_t reg_offset = (reg << 2); local in function:jpeg_v2_0_dec_ring_emit_wreg
650 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
653 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
655 amdgpu_ring_write(ring, reg_offset);
[all...] |
| amdgpu_sdma_v5_0.c | 119 base = adev->reg_offset[GC_HWIP][0][1];
123 base = adev->reg_offset[GC_HWIP][0][0];
1399 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? local in function:sdma_v5_0_set_trap_irq_state
1403 sdma_cntl = RREG32(reg_offset);
1406 WREG32(reg_offset, sdma_cntl);
|
| amdgpu_gfx_v6_0.c | 405 u32 reg_offset, split_equal_to_row_size, *tilemode; local in function:gfx_v6_0_tiling_mode_table_init
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
646 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
851 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
852 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset])
[all...] |
| amdgpu_gfx_v7_0.c | 1037 u32 reg_offset, split_equal_to_row_size; local in function:gfx_v7_0_tiling_mode_table_init
1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1057 tile[reg_offset] = 0;
1058 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1059 macrotile[reg_offset] = 0;
1223 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++
[all...] |
| amdgpu_gfx_v8_0.c | 2104 u32 reg_offset; local in function:gfx_v8_0_tiling_mode_table_init
2109 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2110 modearray[reg_offset] = 0;
2112 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2113 mod2array[reg_offset] = 0;
2277 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++
[all...] |
| amdgpu.h | 558 uint32_t reg_offset; member in struct:amdgpu_allowed_register_entry
578 u32 sh_num, u32 reg_offset, u32 *value);
679 u32 reg_offset; member in struct:amdgpu_mmio_remap
957 const uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; member in struct:amdgpu_device
|
| /src/sys/dev/isa/ |
| nca_isa.c | 123 nca_isa_test(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t reg_offset)
127 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, SCI_ICMD_RST);
128 bus_space_write_1(iot, ioh, reg_offset + C80_ODR, 0);
132 if (bus_space_read_1(iot, ioh, reg_offset + C80_CSBR) != SCI_BUS_RST) {
135 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_CSBR));
137 bus_space_write_1(iot, ioh, reg_offset+C80_ICR, 0);
141 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, 0);
146 bus_space_read_1(iot, ioh, reg_offset + C80_RPIR);
150 if (bus_space_read_1(iot, ioh, reg_offset + C80_BSR) & (SCI_CSR_PERR |
154 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_BSR))
179 bus_size_t base_offset, reg_offset = 0; local in function:nca_isa_find
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni_dma.c | 197 u32 reg_offset, wb_offset; local in function:cayman_dma_resume
203 reg_offset = DMA0_REGISTER_OFFSET;
207 reg_offset = DMA1_REGISTER_OFFSET;
211 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
212 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
220 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
223 WREG32(DMA_RB_RPTR + reg_offset, 0);
224 WREG32(DMA_RB_WPTR + reg_offset, 0);
227 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
229 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
[all...] |
| radeon_cik_sdma.c | 257 u32 rb_cntl, reg_offset; local in function:cik_sdma_gfx_stop
266 reg_offset = SDMA0_REGISTER_OFFSET;
268 reg_offset = SDMA1_REGISTER_OFFSET;
269 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
271 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
272 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
311 uint32_t reg_offset, value; local in function:cik_sdma_ctx_switch_enable
316 reg_offset = SDMA0_REGISTER_OFFSET;
318 reg_offset = SDMA1_REGISTER_OFFSET;
319 value = RREG32(SDMA0_CNTL + reg_offset);
338 u32 me_cntl, reg_offset; local in function:cik_sdma_enable
375 u32 reg_offset, wb_offset; local in function:cik_sdma_gfx_resume
[all...] |
| radeon_si.c | 2505 u32 reg_offset, split_equal_to_row_size; local in function:si_tiling_mode_table_init
2520 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2521 tile[reg_offset] = 0;
2734 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2735 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
[all...] |
| radeon_cik.c | 2354 u32 reg_offset, split_equal_to_row_size; local in function:cik_tiling_mode_table_init
2376 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2377 tile[reg_offset] = 0;
2378 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2379 macrotile[reg_offset] = 0;
2519 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++
[all...] |
| /src/usr.bin/scmdctl/ |
| common.c | 221 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_invert_motor
241 reg_offset = motor_index / 8;
244 reg = SCMD_REG_INV_2_9 + reg_offset;
246 fprintf(stderr,"common_invert_motor: remote invert: motor_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg);
263 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_bridge_motor
276 reg_offset = module_index / 8;
279 reg = SCMD_REG_BRIDGE_SLV_L + reg_offset;
281 fprintf(stderr,"common_bridge_motor: remote bridge: module_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",module_index,reg_offset,reg_index,reg)
[all...] |
| /src/sys/arch/mac68k/obio/ |
| esp.c | 183 unsigned long reg_offset; local in function:espattach
190 reg_offset = SCSIBase - IOBase;
203 switch (reg_offset) {
261 switch (reg_offset) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_pm4_headers_diq.h | 192 unsigned int reg_offset:16; member in struct:pm4__set_config_reg::__anone5b337d8130a::__anone5b337d81408
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsi_vbt.c | 460 u8 reg_offset = *(data + 5); local in function:mipi_exec_i2c
479 payload_data[0] = reg_offset;
491 payload_size, reg_offset);
|
