| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_clocks.c | 48 uint32_t fb_div, ref_div, post_div, sclk; local in function:radeon_legacy_get_engine_clock
61 sclk = fb_div / ref_div;
65 sclk >>= 1;
67 sclk >>= 2;
69 sclk >>= 3;
71 return sclk;
106 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
160 val = of_get_property(dp, "ATY,SCLK", NULL);
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| radeon_i2c.c | 248 u32 sclk = rdev->pm.current_sclk; local in function:radeon_get_i2c_prescale
268 nm = (sclk * 10) / (i2c_clock * 4);
283 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
298 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
300 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
349 /* take the pm lock since we need a constant sclk */
602 /* take the pm lock since we need a constant sclk */
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| rv6xx_dpm.h | 32 /* Represents a single SCLK step. */
82 u32 sclk; member in struct:rv6xx_pl
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| radeon_rs690.c | 274 fixed20_12 sclk; member in struct:rs690_watermark
286 fixed20_12 sclk, core_bandwidth, max_bandwidth; local in function:rs690_crtc_bandwidth_compute
301 /* sclk in Mhz */
303 sclk.full = dfixed_const(selected_sclk);
304 sclk.full = dfixed_div(sclk, a);
306 /* core_bandwidth = sclk(Mhz) * 16 */
308 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
390 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
392 sclk.full = dfixed_mul(max_bandwidth, a)
[all...] |
| radeon_rv515.c | 957 fixed20_12 sclk; member in struct:rv515_watermark
969 fixed20_12 sclk; local in function:rv515_crtc_bandwidth_compute
985 /* sclk in Mhz */
987 sclk.full = dfixed_const(selected_sclk);
988 sclk.full = dfixed_div(sclk, a);
1052 * sclk = system clock(Mhz)
1055 chunk_time.full = dfixed_div(a, sclk);
1140 fill_rate.full = dfixed_div(wm0->sclk, a);
1188 fill_rate.full = dfixed_div(wm0->sclk, a)
[all...] |
| trinity_dpm.h | 33 u32 sclk; member in struct:trinity_pl
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| radeon_device.c | 752 * Used when sclk/mclk are switched or display modes are set.
758 u32 sclk = rdev->pm.current_sclk; local in function:radeon_update_bandwidth_info
761 /* sclk/mclk in Mhz */
763 rdev->pm.sclk.full = dfixed_const(sclk);
764 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
770 /* core_bandwidth = sclk(Mhz) * 16 */
771 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
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| radeon_pm.c | 191 u32 sclk, mclk; local in function:radeon_set_power_state
199 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].sclk;
201 if (sclk > rdev->pm.default_sclk)
202 sclk = rdev->pm.default_sclk;
223 if (sclk < rdev->pm.current_sclk)
240 if (sclk != rdev->pm.current_sclk) {
242 radeon_set_engine_clock(rdev, sclk);
244 rdev->pm.current_sclk = sclk;
245 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
[all...] |
| radeon_rs780_dpm.c | 758 u32 sclk; local in function:rs780_parse_pplib_clock_info
760 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
761 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
762 ps->sclk_low = sclk;
763 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
764 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
765 ps->sclk_high = sclk;
952 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
954 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
998 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) local in function:rs780_dpm_debugfs_print_current_performance_level
1021 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) \/ local in function:rs780_dpm_get_current_sclk
[all...] |
| rv770_smc.h | 110 RV770_SMC_SCLK_VALUE sclk; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
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| kv_dpm.h | 73 u32 sclk; member in struct:kv_pl
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| rv770_dpm.h | 145 u32 sclk; member in struct:rv7xx_pl
184 RV770_SMC_SCLK_VALUE *sclk);
205 RV770_SMC_SCLK_VALUE *sclk);
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| sumo_dpm.h | 35 u32 sclk; member in struct:sumo_pl
210 u32 sclk,
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_nv40.c | 155 int sclk = cstate->domain[nv_clk_src_shader]; local in function:nv40_clk_calc
174 if (sclk && sclk != gclk) {
175 ret = nv40_clk_calc_pll(clk, 0x004008, sclk,
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| nouveau_nvkm_subdev_clk_gf100.c | 72 u32 sclk; local in function:read_pll
80 sclk = device->crystal;
84 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
87 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
93 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
99 return sclk * N / M / P;
107 u32 sclk, sctl, sdiv = 2; local in function:read_div
117 sclk = read_vco(clk, dsrc + (doff * 4));
131 return (sclk * 2) / sdiv;
143 u32 sclk, sdiv local in function:read_clk
228 u32 sclk; local in function:calc_src
[all...] |
| nouveau_nvkm_subdev_clk_gk104.c | 73 u32 sclk; local in function:read_pll
82 sclk = device->crystal;
86 sclk = read_pll(clk, 0x132020);
90 sclk = read_div(clk, 0, 0x137320, 0x137330);
97 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
106 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
107 return sclk / (M * P);
126 u32 sclk = read_vco(clk, dsrc + (doff * 4)) local in function:read_div
154 u32 sclk, sdiv; local in function:read_clk
241 u32 sclk; local in function:calc_src
[all...] |
| nouveau_nvkm_subdev_clk_gt215.c | 69 u32 sctl, sdiv, sclk; local in function:read_clk
104 sclk = read_vco(clk, idx);
106 return (sclk * 2) / sdiv;
117 u32 sclk = 0, P = 1, N = 1, M = 1; local in function:read_pll
133 sclk = read_clk(clk, 0x00 + idx, false);
136 sclk = read_clk(clk, 0x10 + idx, false);
144 return sclk * N / MP;
196 u32 oclk, sclk, sdiv; local in function:gt215_clk_info
212 sclk = read_vco(clk, idx);
213 sdiv = min((sclk * 2) / khz, (u32)65)
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| cpu.c | 482 uint64_t clk, sclk = 0; local in function:cpu_attach
541 sclk = prom_getpropint(findroot(), "stick-frequency", 0);
543 ci->ci_system_clockrate[0] = sclk;
544 ci->ci_system_clockrate[1] = sclk / 1000000;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 107 struct bw_fixed sclk[8]; local in function:calculate_bandwidth
134 sclk[s_low] = vbios->low_sclk;
135 sclk[s_mid1] = vbios->mid1_sclk;
136 sclk[s_mid2] = vbios->mid2_sclk;
137 sclk[s_mid3] = vbios->mid3_sclk;
138 sclk[s_mid4] = vbios->mid4_sclk;
139 sclk[s_mid5] = vbios->mid5_sclk;
140 sclk[s_mid6] = vbios->mid6_sclk;
141 sclk[s_high] = vbios->high_sclk;
1074 /*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pm.c | 296 * level which varies from asic to asic. profile_min_sclk forces the sclk
298 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
677 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
682 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
698 * They can be used to calibrate the sclk voltage curve.
700 * - a list of valid ranges for sclk, mclk, and voltage curve points
710 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
713 * For sclk voltage curve, enter the new values by writing a
976 * will enable sclk levels 4, 5, and 6.
2569 uint32_t sclk; local in function:amdgpu_hwmon_show_sclk
[all...] |
| kv_dpm.h | 99 u32 sclk; member in struct:kv_pl
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 65 struct dm_pp_clock_range sclk; member in struct:dm_pp_gpu_clock_range
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 851 pr_info("Currently sclk only support 3 levels on RV\n");
1127 uint32_t sclk, mclk; local in function:smu10_read_sensor
1133 sclk = smum_get_argument(hwmgr);
1135 *((uint32_t *)value) = sclk * 100;
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| amdgpu_smu8_hwmgr.c | 270 table->sclk = dep_table->entries[dep_table->count-1].clk;
727 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
1275 * switching SCLK from DPM 0 to 6/7 */
1488 info->engine_max_clock = limits->sclk;
1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local in function:smu8_read_sensor
1709 sclk = table->entries[sclk_index].clk;
1710 *((uint32_t *)value) = sclk;
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 178 unsigned long sclk; member in struct:pp_clock_engine_request
|
