| /src/sbin/chkconfig/ |
| chkconfig.sh | 56 _name=$1
57 load_rc_config ${_name}
58 if checkyesno ${_name}; then
59 printf "\t%-15s\t\ton\n" ${_name}
62 printf "\t%-15s\t\toff\n" ${_name}
72 _name=$1
73 fqp="/etc/rc.d/${_name}"
87 _name=$1
88 fqp="/etc/rc.d/${_name}"
119 _name=$
[all...] |
| /src/sys/arch/arm/fdt/ |
| arm_fdtvar.h | 41 #define _ARM_CPU_METHOD_REGISTER(_name) \
42 __link_set_add_rodata(arm_cpu_methods, __CONCAT(_name,_cpu_method));
44 #define ARM_CPU_METHOD(_name, _compat, _enable) \
45 static const struct arm_cpu_method __CONCAT(_name,_cpu_method) = { \
49 _ARM_CPU_METHOD_REGISTER(_name)
|
| /src/sys/dev/fdt/ |
| fdt_opp.h | 40 #define FDT_OPP(_name, _compat, _suppfn) \
41 static const struct fdt_opp_info __CONCAT(_name,_oppinfo) = { \
45 _FDT_OPP_REGISTER(_name)
|
| fdt_console.h | 46 #define FDT_CONSOLE(_name, _ops) \
47 static const struct fdt_console_info __CONCAT(_name,_consinfo) = { \
50 _FDT_CONSOLE_REGISTER(_name)
|
| fdt_platform.h | 62 #define FDT_PLATFORM(_name, _compat, _ops) \
63 static const struct fdt_platform_info __CONCAT(_name,_platinfo) = { \
67 _FDT_PLATFORM_REGISTER(_name)
|
| /src/sys/arch/ia64/stand/common/ |
| bitstring.h | 76 register bitstr_t *_name = (name); \
81 _name[_startbyte] &= ((0xff >> (8 - (_start&0x7))) | \
84 _name[_startbyte] &= 0xff >> (8 - (_start&0x7)); \
86 _name[_startbyte] = 0; \
87 _name[_stopbyte] &= 0xff << ((_stop&0x7) + 1); \
93 register bitstr_t *_name = (name); \
98 _name[_startbyte] |= ((0xff << (_start&0x7)) & \
101 _name[_startbyte] |= 0xff << ((_start)&0x7); \
103 _name[_startbyte] = 0xff; \
104 _name[_stopbyte] |= 0xff >> (7 - (_stop&0x7));
[all...] |
| /src/include/ |
| bitstring.h | 95 bitstr_t *_name = name; \
98 bit_clear(_name, _start); \
105 bitstr_t *_name = name; \
108 bit_set(_name, _start); \
115 const bitstr_t *_name = name; \
119 if (!bit_test(_name, _bit)) { \
128 const bitstr_t *_name = name; \
132 if (bit_test(_name, _bit)) { \
|
| /src/sys/arch/arm/nxp/ |
| imx_ccm.h | 61 #define IMX_EXTCLK(_id, _name) \
65 .base.name = (_name), \
67 .u.extclk = (_name), \
87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \
94 .base.name = (_name), \
102 #define IMX_ROOT_GATE(_id, _name, _pname, _reg) \
103 IMX_ROOT_GATE_INDEX(_id, 0, _name, _pname, _reg)
104 #define IMX_ROOT_GATE_INDEX(_id, _regidx, _name, _pname, _reg)
[all...] |
| imx6_ccmvar.h | 161 #define CLK_FIXED(_name, _rate) { \
162 .base = { .name = (_name) }, \
171 #define CLK_FIXED_FACTOR(_name, _parent, _div, _mult) { \
172 .base = { .name = (_name) }, \
183 #define CLK_PFD(_name, _parent, _reg, _index) { \
184 .base = { .name = (_name) }, \
195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
196 .base = { .name = (_name) }, \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
211 .base = { .name = (_name) }, \
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 111 #define RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, _flags) \
115 .base.name = (_name), \
131 #define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
132 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, 0)
134 #define RK3288_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
135 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3288)
137 #define RK3588_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
138 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3588)
190 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \
194 .base.name = (_name), \
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 79 #define MESON_CLK_FIXED(_id, _name, _rate) \
82 .base.name = (_name), \
105 #define MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, _flags) \
108 .base.name = (_name), \
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \
119 MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, 0)
142 #define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \
145 .base.name = (_name), \
172 #define MESON_CLK_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
175 .base.name = (_name), \
[all...] |
| /src/sys/arch/riscv/starfive/ |
| jh71x0_clkc.h | 111 #define JH71X0CLKC_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
114 .jcc_clk.name = (_name), \
137 #define JH71X0CLKC_GATE(_id, _name, _pname) \
141 .name = (_name), \
171 #define JH71X0CLKC_DIV_FLAGS(_id, _name, _maxdiv, _parent, _flags) \
175 .name = (_name), \
213 #define JH71X0CLKC_FRACDIV(_id, _name, _parent) \
217 .name = (_name), \
246 #define JH71X0CLKC_MUX_FLAGSX2(_id, _name, _parents, _cflags, _mflags) \
250 .name = (_name), \
[all...] |
| /src/sys/arch/arm/ti/ |
| ti_prcm.h | 97 #define TI_PRCM_FIXED(_name, _rate) \
99 .type = TI_PRCM_FIXED, .base.name = (_name), \
126 #define TI_PRCM_FIXED_FACTOR(_name, _mult, _div, _parent) \
128 .type = TI_PRCM_FIXED_FACTOR, .base.name = (_name), \
143 #define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \
144 TI_PRCM_HWMOD_MASK(_name, _reg, 0, _parent, _enable, 0)
146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \
148 .type = TI_PRCM_HWMOD, .base.name = (_name), \
|
| omap3_cm.c | 91 #define OMAP3_CM_HWMOD_CORE1(_name, _bit, _parent, _flags) \
92 TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
93 #define OMAP3_CM_HWMOD_CORE3(_name, _bit, _parent, _flags) \
94 TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
95 #define OMAP3_CM_HWMOD_WKUP(_name, _bit, _parent, _flags) \
96 TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
97 #define OMAP3_CM_HWMOD_PER(_name, _bit, _parent, _flags) \
98 TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
99 #define OMAP3_CM_HWMOD_USBHOST(_name, _bit, _parent, _flags) \
100 TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)
[all...] |
| am3_prcm.c | 129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \
130 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable)
131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \
132 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display)
133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \
134 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable)
|
| /src/sys/net80211/ |
| ieee80211_netbsd.h | 43 #define IEEE80211_LOCK_INIT_IMPL(_ic, _name, _member) \
61 #define IEEE80211_BEACON_LOCK_INIT(_ic, _name) \
62 IEEE80211_LOCK_INIT_IMPL(_ic, _name, ic_beaconlock)
77 #define IEEE80211_NODE_LOCK_INIT(_nt, _name) \
78 IEEE80211_LOCK_INIT_IMPL(_nt, _name, nt_nodelock)
94 #define IEEE80211_SCAN_LOCK_INIT(_nt, _name) \
95 IEEE80211_LOCK_INIT_IMPL(_nt, _name, nt_scanlock)
108 #define IEEE80211_NODE_SAVEQ_INIT(_ni, _name) do { \
148 #define ACL_LOCK_INIT(_as, _name) \
149 IEEE80211_LOCK_INIT_IMPL(_as, _name, as_lock
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_validation.h | 100 * @_name: The name of the variable
108 #define DECLARE_VAL_CONTEXT(_name, _ht, _merge_dups) \
109 struct vmw_validation_context _name = \
111 .resource_list = LIST_HEAD_INIT((_name).resource_list), \
112 .resource_ctx_list = LIST_HEAD_INIT((_name).resource_ctx_list), \
113 .bo_list = LIST_HEAD_INIT((_name).bo_list), \
114 .page_list = LIST_HEAD_INIT((_name).page_list), \
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \
84 .base.name = (_name), \
129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
133 .base.name = (_name), \
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \
152 SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
182 #define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \
186 .base.name = (_name), \
228 #define SUNXI_CCU_DIV(_id, _name, _parents, _reg, _div, \
230 SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div,
[all...] |
| /src/sbin/newfs_msdos/ |
| mkfs_msdos.h | 60 #define AOPT(_opt, _type, _name, _min, _desc) _type _name;
|
| /src/usr.bin/sys_info/ |
| sys_info.sh | 61 local IFS _var _name _d -
64 _var="$1"; _name="$2"
74 if [ -f "$_d/$_name" ] && [ -x "$_d/$_name" ]; then
76 eval $_var=\""$_d/$_name"\"
|
| /src/sys/arch/mips/include/ |
| signal.h | 90 #define _SIGCONTEXT_DEFINE(_name, _reg_t, _fp_t) \
|
| /src/sys/arch/arm/nvidia/ |
| tegra210_car.c | 304 #define CLK_FIXED(_name, _rate) { \
305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
322 #define CLK_MUX(_name, _reg, _bits, _p) { \
323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
334 #define CLK_FIXED_DIV(_name, _parent, _div) { \
335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV,
[all...] |
| tegra124_car.c | 292 #define CLK_FIXED(_name, _rate) { \
293 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
298 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
310 #define CLK_MUX(_name, _reg, _bits, _p) { \
311 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
322 #define CLK_FIXED_DIV(_name, _parent, _div) { \
323 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \
333 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV,
[all...] |
| /src/sys/arch/hpc/stand/hpcboot/menu/ |
| tabwindow.h | 81 const TCHAR *_name; member in class:TabWindow
84 : Window(base._app, base._window), _base(base), _name(name) {
|
| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 131 #define CLK_FIXED(_name, _rate) { \
132 .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \
136 #define CLK_PLL(_name, _parent, _lock, _con0) { \
137 .base = { .name = (_name) }, .type = EXYNOS_CLK_PLL, \
147 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
148 .base = { .name = (_name), .flags = (_f) }, \
161 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
162 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
164 #define CLK_MUX(_name, _reg, _bits, _p) \
165 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p
[all...] |
