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    Searched refs:AcpLevel (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7_fusion.h 239 SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
smu7_discrete.h 332 SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
smu72_discrete.h 274 SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
smu73_discrete.h 258 SMU73_Discrete_ExtClkLevel AcpLevel [SMU73_MAX_LEVELS_ACP];
smu74_discrete.h 290 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
smu75_discrete.h 296 SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 239 SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
smu7_discrete.h 331 SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
radeon_ci_dpm.c 2741 table->AcpLevel[count].Frequency =
2743 table->AcpLevel[count].MinVoltage =
2745 table->AcpLevel[count].MinPhases = 1;
2749 table->AcpLevel[count].Frequency, false, &dividers);
2753 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2755 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2756 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
radeon_kv_dpm.c 1071 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1479 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
1480 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1482 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1484 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1488 table->AcpLevel[count].Frequency, &dividers);
1492 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1494 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1495 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
amdgpu_tonga_smumgr.c 1434 table->AcpLevel[count].Frequency =
1436 table->AcpLevel[count].MinVoltage.Vddc =
1439 table->AcpLevel[count].MinVoltage.VddGfx =
1443 table->AcpLevel[count].MinVoltage.Vddci =
1446 table->AcpLevel[count].MinVoltage.Phases = 1;
1450 table->AcpLevel[count].Frequency, &dividers);
1454 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1456 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
amdgpu_ci_smumgr.c 1607 table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;
1608 table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
1609 table->AcpLevel[count].MinPhases = 1;
1612 table->AcpLevel[count].Frequency, &dividers);
1616 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1618 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1619 CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 1154 offsetof(SMU7_Fusion_DpmTable, AcpLevel),

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