HomeSort by: relevance | last modified time | path
    Searched refs:CG_SPLL_FUNC_CNTL (Results 1 - 24 of 24) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h 28 #define CG_SPLL_FUNC_CNTL 0x600
rv730d.h 28 #define CG_SPLL_FUNC_CNTL 0x600
rs780d.h 28 #define CG_SPLL_FUNC_CNTL 0x600
radeon_rs780_dpm.c 217 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
994 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1017 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
radeon_rv740_dpm.c 130 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
293 pi->clk_regs.rv770.cg_spll_func_cntl =
294 RREG32(CG_SPLL_FUNC_CNTL);
327 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
radeon_r600_dpm.c 327 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
329 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
337 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
radeon_rv730_dpm.c 50 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
206 pi->clk_regs.rv730.cg_spll_func_cntl =
207 RREG32(CG_SPLL_FUNC_CNTL);
291 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
350 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
rv770d.h 91 #define CG_SPLL_FUNC_CNTL 0x600
radeon_si.c 3998 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4000 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4029 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4031 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4033 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4035 WREG32(CG_SPLL_FUNC_CNTL, tmp);
nid.h 540 #define CG_SPLL_FUNC_CNTL 0x600
cikd.h 250 #define CG_SPLL_FUNC_CNTL 0xC0500140
sid.h 87 #define CG_SPLL_FUNC_CNTL 0x600
evergreend.h 76 #define CG_SPLL_FUNC_CNTL 0x600
r600d.h 1272 #define CG_SPLL_FUNC_CNTL 0x600
radeon_rv770_dpm.c 495 pi->clk_regs.rv770.cg_spll_func_cntl;
933 pi->clk_regs.rv770.cg_spll_func_cntl;
1057 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1525 pi->clk_regs.rv770.cg_spll_func_cntl =
1526 RREG32(CG_SPLL_FUNC_CNTL);
radeon_ni_dpm.c 1189 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1716 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
1806 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
2009 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
radeon_ci_dpm.c 1880 pi->clock_registers.cg_spll_func_cntl =
1881 RREG32_SMC(CG_SPLL_FUNC_CNTL);
3001 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
radeon_si_dpm.c 3576 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4403 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4498 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4792 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 892 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
894 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1350 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1352 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
amdgpu_iceland_smumgr.c 831 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
833 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
1467 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
1469 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
amdgpu_ci_smumgr.c 330 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
332 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1419 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
1421 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
amdgpu_tonga_smumgr.c 574 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
576 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
1215 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1217 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 89 #define CG_SPLL_FUNC_CNTL 0x180
amdgpu_si_dpm.c 4037 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4869 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4962 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5256 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

Completed in 75 milliseconds