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    Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 - 21 of 21) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h 36 #define CG_SPLL_FUNC_CNTL_2 0x604
rv730d.h 39 #define CG_SPLL_FUNC_CNTL_2 0x604
radeon_rv740_dpm.c 131 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
295 pi->clk_regs.rv770.cg_spll_func_cntl_2 =
296 RREG32(CG_SPLL_FUNC_CNTL_2);
328 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
radeon_rv730_dpm.c 51 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
208 pi->clk_regs.rv730.cg_spll_func_cntl_2 =
209 RREG32(CG_SPLL_FUNC_CNTL_2);
292 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
352 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
radeon_rv770.c 1150 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1153 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1162 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
rv770d.h 102 #define CG_SPLL_FUNC_CNTL_2 0x604
nid.h 549 #define CG_SPLL_FUNC_CNTL_2 0x604
cikd.h 259 #define CG_SPLL_FUNC_CNTL_2 0xC0500144
sid.h 96 #define CG_SPLL_FUNC_CNTL_2 0x604
radeon_si.c 4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4012 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4014 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
evergreend.h 84 #define CG_SPLL_FUNC_CNTL_2 0x604
radeon_rv770_dpm.c 497 pi->clk_regs.rv770.cg_spll_func_cntl_2;
935 pi->clk_regs.rv770.cg_spll_func_cntl_2;
1059 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1527 pi->clk_regs.rv770.cg_spll_func_cntl_2 =
1528 RREG32(CG_SPLL_FUNC_CNTL_2);
radeon_ni_dpm.c 1190 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
1718 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
1807 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
2010 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
radeon_ci_dpm.c 1882 pi->clock_registers.cg_spll_func_cntl_2 =
1883 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
3002 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
radeon_si_dpm.c 3577 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4405 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4499 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4793 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 98 #define CG_SPLL_FUNC_CNTL_2 0x181
amdgpu_si_dpm.c 4038 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4871 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4963 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5257 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1354 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
amdgpu_iceland_smumgr.c 1471 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
amdgpu_ci_smumgr.c 1423 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
amdgpu_tonga_smumgr.c 1219 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,

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