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    Searched refs:CG_SPLL_FUNC_CNTL_3 (Results 1 - 19 of 19) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h 39 #define CG_SPLL_FUNC_CNTL_3 0x608
rv730d.h 42 #define CG_SPLL_FUNC_CNTL_3 0x608
radeon_rv740_dpm.c 132 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
297 pi->clk_regs.rv770.cg_spll_func_cntl_3 =
298 RREG32(CG_SPLL_FUNC_CNTL_3);
329 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
radeon_rv730_dpm.c 52 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
210 pi->clk_regs.rv730.cg_spll_func_cntl_3 =
211 RREG32(CG_SPLL_FUNC_CNTL_3);
293 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
354 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
rv770d.h 106 #define CG_SPLL_FUNC_CNTL_3 0x608
nid.h 552 #define CG_SPLL_FUNC_CNTL_3 0x608
cikd.h 262 #define CG_SPLL_FUNC_CNTL_3 0xC0500148
sid.h 101 #define CG_SPLL_FUNC_CNTL_3 0x608
evergreend.h 88 #define CG_SPLL_FUNC_CNTL_3 0x608
radeon_rv770_dpm.c 499 pi->clk_regs.rv770.cg_spll_func_cntl_3;
937 pi->clk_regs.rv770.cg_spll_func_cntl_3;
1061 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1529 pi->clk_regs.rv770.cg_spll_func_cntl_3 =
1530 RREG32(CG_SPLL_FUNC_CNTL_3);
radeon_ni_dpm.c 1191 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
1720 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
1808 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
2011 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
radeon_ci_dpm.c 1884 pi->clock_registers.cg_spll_func_cntl_3 =
1885 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
3036 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3171 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
radeon_si_dpm.c 3578 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4407 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4500 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4794 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 898 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
902 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
amdgpu_iceland_smumgr.c 837 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
841 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
amdgpu_ci_smumgr.c 336 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
340 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
amdgpu_tonga_smumgr.c 580 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
584 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 103 #define CG_SPLL_FUNC_CNTL_3 0x182
amdgpu_si_dpm.c 4039 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4873 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4964 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5258 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

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