Searched refs:CLK_TOP_AUD_1_SEL (Results 1 - 9 of 9) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt6765-clk.h150 #define CLK_TOP_AUD_1_SEL 113 macro
H A Dmt8173-clk.h121 #define CLK_TOP_AUD_1_SEL 109 macro
H A Dmediatek,mt6795-clk.h118 #define CLK_TOP_AUD_1_SEL 105 macro
H A Dmt2712-clk.h158 #define CLK_TOP_AUD_1_SEL 125 macro
H A Dmt8192-clk.h61 #define CLK_TOP_AUD_1_SEL 47 macro
H A Dmediatek,mt8365-clk.h90 #define CLK_TOP_AUD_1_SEL 78 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi831 <&topckgen CLK_TOP_AUD_1_SEL>,
H A Dmt8173.dtsi886 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
H A Dmt8192.dtsi1010 <&topckgen CLK_TOP_AUD_1_SEL>,

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