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    Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
mt7629-clk.h 96 #define CLK_TOP_MSDC50_0_SEL 84
mt6765-clk.h 146 #define CLK_TOP_MSDC50_0_SEL 109
mt7622-clk.h 81 #define CLK_TOP_MSDC50_0_SEL 67
mt8173-clk.h 108 #define CLK_TOP_MSDC50_0_SEL 96
mt2712-clk.h 145 #define CLK_TOP_MSDC50_0_SEL 112
mt8192-clk.h 38 #define CLK_TOP_MSDC50_0_SEL 24
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt7622.dtsi 687 <&topckgen CLK_TOP_MSDC50_0_SEL>;
mt8173-elm.dtsi 382 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

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