Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 - 14 of 14) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt7629-clk.h96 #define CLK_TOP_MSDC50_0_SEL 84 macro
H A Dmt6765-clk.h146 #define CLK_TOP_MSDC50_0_SEL 109 macro
H A Dmt7622-clk.h81 #define CLK_TOP_MSDC50_0_SEL 67 macro
H A Dmt8173-clk.h108 #define CLK_TOP_MSDC50_0_SEL 96 macro
H A Dmediatek,mt6795-clk.h106 #define CLK_TOP_MSDC50_0_SEL 93 macro
H A Dmt2712-clk.h145 #define CLK_TOP_MSDC50_0_SEL 112 macro
H A Dmt8192-clk.h38 #define CLK_TOP_MSDC50_0_SEL 24 macro
H A Dmediatek,mt8365-clk.h85 #define CLK_TOP_MSDC50_0_SEL 73 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8365-evk.dts166 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt7622.dtsi704 <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt6795.dtsi684 <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8365.dtsi662 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
H A Dmt8173-elm.dtsi394 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8192.dtsi1396 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,

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