Searched refs:CLK_TOP_UNIVPLL_D5_D4 (Results 1 - 9 of 9) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt6779-clk.h83 #define CLK_TOP_UNIVPLL_D5_D4 71 macro
H A Dmt8183-clk.h108 #define CLK_TOP_UNIVPLL_D5_D4 70 macro
H A Dmt8192-clk.h107 #define CLK_TOP_UNIVPLL_D5_D4 93 macro
H A Dmt8186-clk.h113 #define CLK_TOP_UNIVPLL_D5_D4 92 macro
H A Dmediatek,mt8188-clk.h131 #define CLK_TOP_UNIVPLL_D5_D4 118 macro
H A Dmt8195-clk.h164 #define CLK_TOP_UNIVPLL_D5_D4 150 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8188.dtsi1474 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1475 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1580 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1581 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1598 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1599 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
H A Dmt8195.dtsi1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1379 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1454 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1455 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1477 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1493 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1509 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1525 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
H A Dmt8192.dtsi957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;

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