| /src/sys/arch/evbarm/stand/boot2440/ |
| dm9000.c | 148 CSR_WRITE_1(struct local *l, int reg, int data)
200 CSR_WRITE_1(l, NCR, 0); /* use internal PHY */
204 CSR_WRITE_1(l, GPR, GPR_PHYPWROFF);
206 CSR_WRITE_1(l, IMR, 0);
207 CSR_WRITE_1(l, TCR, 0);
208 CSR_WRITE_1(l, RCR, 0);
211 CSR_WRITE_1(l, NCR, NCR_RST);
217 CSR_WRITE_1(l, GPR, 0);
220 CSR_WRITE_1(l, NCR, NCR_RST);
230 CSR_WRITE_1(l, PAR + 0, en[0])
[all...] |
| /src/sys/arch/sandpoint/stand/altboot/ |
| dsk.c | 60 #define CSR_WRITE_1(r,v) out8(r,v)
184 CSR_WRITE_1(chan->ctl, ATA_DREQ);
186 CSR_WRITE_1(chan->ctl, ATA_SRST|ATA_DREQ);
188 CSR_WRITE_1(chan->ctl, ATA_DREQ);
199 CSR_WRITE_1(chan->cmd + _NSECT, 0);
200 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_IDLE);
203 CSR_WRITE_1(chan->cmd + _NSECT, 0);
204 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_STANDBY);
214 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_CHKPWR);
227 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_IDENT)
[all...] |
| vge.c | 47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
230 CSR_WRITE_1(l, VR_CTL1, val);
276 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR);
277 CSR_WRITE_1(l, VR_CAMADR, CAM_EN | SADR_CAM | 0);
279 CSR_WRITE_1(l, VR_CAM0 + i, en[i]);
280 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR | CAMCTL_WR);
285 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_VBIT);
286 CSR_WRITE_1(l, VR_CAM0, 01);
288 CSR_WRITE_1(l, VR_CAM0 + i, 00);
289 CSR_WRITE_1(l, VR_CAMADR, 0)
[all...] |
| nvt.c | 47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
183 CSR_WRITE_1(l, VR_CTL1, val);
230 CSR_WRITE_1(l, VR_RCR, 0);
231 CSR_WRITE_1(l, VR_TCR, 0);
235 CSR_WRITE_1(l, VR_CTL1, CTL1_FDX);
236 CSR_WRITE_1(l, VR_CTL0, CTL0_START);
237 CSR_WRITE_1(l, VR_CTL0, l->ctl0);
259 CSR_WRITE_1(l, VR_CTL0, l->ctl0 | CTL0_TDMD);
319 CSR_WRITE_1(l, VR_MIICR, 0);
324 CSR_WRITE_1(l, VR_MIICR, MIICR_MAUTO)
[all...] |
| fxp.c | 89 #define CSR_WRITE_1(l, r, v) out8((l)->iobase+(r), (v))
221 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
224 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
277 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
300 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
352 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
373 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_RESUME);
401 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_RESUME);
|
| rge.c | 47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
159 CSR_WRITE_1(l, RGE_CR, CR_RESET);
171 CSR_WRITE_1(l, RGE_EECMD, EECMD_UNLOCK);
176 CSR_WRITE_1(l, RGE_EECMD, EECMD_LOCK);
218 CSR_WRITE_1(l, RGE_CR, CR_TXEN | CR_RXEN);
219 CSR_WRITE_1(l, RGE_ETTHR, 0x3f);
254 CSR_WRITE_1(l, RGE_TPPOLL, 0x40);
|
| stg.c | 41 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
207 CSR_WRITE_1(l, STGE_StationAddress0 + i, en[i]);
397 CSR_WRITE_1(l, STGE_PhyCtrl, v);
509 CSR_WRITE_1(l, STGE_PhyCtrl, v);
522 CSR_WRITE_1(l, STGE_PhyCtrl, v);
529 CSR_WRITE_1(l, STGE_PhyCtrl, v);
539 CSR_WRITE_1(l, STGE_PhyCtrl, v | PC_MgmtClk);
541 CSR_WRITE_1(l, STGE_PhyCtrl, v);
|
| skg.c | 46 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
251 CSR_WRITE_1(l, SK_RXMF1_CTRL_TEST, RFCTL_RESET_CLEAR);
253 CSR_WRITE_1(l, SK_TXMF1_CTRL_TEST, TFCTL_RESET_CLEAR);
289 CSR_WRITE_1(l, SK_TXAR1_COUNTERCTL, TXARCTL_ON|TXARCTL_FSYNC_ON);
|
| /src/sys/dev/ic/ |
| com.c | 139 #define CSR_WRITE_1(r, o, v) \
483 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
484 CSR_WRITE_1(regs, COM_REG_IIR, 0);
517 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
519 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);
572 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
640 CSR_WRITE_1(regsp, COM_REG_FIFO,
648 CSR_WRITE_1(regsp, COM_REG_FIFO,
661 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
665 CSR_WRITE_1(regsp, COM_REG_FIFO
[all...] |
| rtl81x9.c | 146 CSR_WRITE_1(sc, RTK_EECMD, \
150 CSR_WRITE_1(sc, RTK_EECMD, \
194 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM);
217 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
229 CSR_WRITE_1(sc, RTK_MII, \
233 CSR_WRITE_1(sc, RTK_MII, \
600 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
1353 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]);
1369 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1415 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB)
[all...] |
| rtl8169.c | 425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
441 CSR_WRITE_1(sc, RTK_LDPS, 1);
779 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
1506 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1828 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
1830 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1917 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
1924 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
1955 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1967 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16)
[all...] |
| wivar.h | 236 #define CSR_WRITE_1(sc, reg, val) \
258 #define CSR_WRITE_1(sc, reg, val) \
|
| rtl81x9var.h | 282 #define CSR_WRITE_1(sc, reg, val) \
|
| i82557var.h | 358 #define CSR_WRITE_1(sc, reg, val) \
|
| i82557.c | 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
1089 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1101 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
2008 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI);
|
| /src/sys/dev/pci/ |
| if_vge.c | 264 #define CSR_WRITE_1(sc, reg, val) \
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
380 CSR_WRITE_1(sc, VGE_EEADDR, addr);
411 CSR_WRITE_1(sc, VGE_MIICMD, 0);
432 CSR_WRITE_1(sc, VGE_MIICMD, 0);
433 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
449 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
480 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
518 CSR_WRITE_1(sc, VGE_MIIADDR, reg)
[all...] |
| if_ipwreg.h | 322 #define CSR_WRITE_1(sc, reg, val) \
340 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
| if_stge.c | 227 #define CSR_WRITE_1(_sc, reg, val) \
1556 CSR_WRITE_1(sc, STGE_StationAddress0 + i,
1591 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
1594 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
1600 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
1601 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
1607 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
1608 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2028 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
|
| if_iwireg.h | 546 #define CSR_WRITE_1(sc, reg, val) \
564 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
|
| if_vr.c | 290 #define CSR_WRITE_1(sc, reg, val) \
329 CSR_WRITE_1(sc, reg, \
333 CSR_WRITE_1(sc, reg, \
383 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM);
394 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
406 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
477 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
517 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
|
| if_msk.c | 277 CSR_WRITE_1(sc, reg, x);
945 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
948 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
949 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
952 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
954 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1024 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
1025 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
1031 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
1032 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR)
[all...] |
| if_ale.c | 1398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
1663 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
1664 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
|
| /src/sys/dev/sdmmc/ |
| sbt.c | 40 #define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val))
188 CSR_WRITE_1(sc, SBT_REG_IENA, ISTAT_INTRD);
300 CSR_WRITE_1(sc, SBT_REG_RPC, 0);
304 CSR_WRITE_1(sc, SBT_REG_RPC, RPC_PCRRT);
310 CSR_WRITE_1(sc, SBT_REG_RPC, 0);
332 CSR_WRITE_1(sc, SBT_REG_ICLR, status);
|
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 65 #define CSR_WRITE_1(sc, reg, val) \
|
| /src/sys/arch/arm/xscale/ |
| pxa2x0_mci.c | 147 #define CSR_WRITE_1(sc, reg, val) \
986 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++);
|
