| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_dsp32mult_dr_m_i.s | 16 R4.L = R0.H * R0.L (IS);
17 R5.H = R0.L * R1.L (IS);
18 R6.L = R1.L * R0.H (IS);
19 R7.L = R1.L * R1.L (IS);
20 R0.H = R0.L * R0.L (IS);
21 R1.L = R0.L * R1.L (IS);
22 R2.L = R1.H * R0.L (IS);
23 R3.H = R1.L * R1.L (IS);
41 R5.H = R2.L * R2.L (IS);
42 R6.L = R2.L * R3.H (IS);
[all...] |
| c_dsp32mult_dr_i.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS);
17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS);
18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS);
19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS);
20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS);
21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS);
22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS);
23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS);
41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS);
42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS);
[all...] |
| c_dsp32mult_pair_m_i.s | 16 R0 = R0.L * R0.L (IS);
17 R2 = R0.L * R1.H (IS);
18 R4 = R1.H * R1.H (IS);
19 R6 = R0.L * R0.L (IS);
37 R0 = R2.L * R2.L (IS);
38 R2 = R2.L * R3.H (IS);
39 R4 = R3.H * R2.H (IS);
40 R6 = R2.L * R3.L (IS);
58 R0 = R4.L * R4.L (IS);
59 R2 = R4.L * R5.H (IS);
[all...] |
| c_dsp32mult_pair_i.s | 16 R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS);
17 R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS);
18 R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS);
19 R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS);
37 R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS);
38 R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS);
39 R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS);
40 R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS);
58 R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS);
59 R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS);
[all...] |
| c_dsp32mac_dr_a0_i.s | 22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS);
24 A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS);
26 A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS);
28 A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS);
48 R0.L = ( A0 -= R1.L * R0.L ) (IS);
50 R2.L = ( A0 += R2.L * R3.H ) (IS);
52 R4.L = ( A0 = R4.H * R5.L ) (IS);
54 R6.L = ( A0 -= R6.H * R7.H ) (IS);
74 R0.L = ( A0 = R1.L * R0.L ) (IS);
76 R2.L = ( A0 -= R2.H * R3.L ) (IS);
[all...] |
| c_dsp32mac_dr_a1_i.s | 21 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS);
23 R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
25 R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS);
27 R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS);
47 R0.H = ( A1 = R1.L * R0.L ) (IS);
49 R2.H = ( A1 += R2.L * R3.H ) (IS);
51 R4.H = ( A1 = R4.H * R5.L ) (IS);
53 R6.H = ( A1 = R6.H * R7.H ) (IS);
73 R0.H = A1 , A0 = R1.L * R0.L (IS);
75 R2.H = A1 , A0 = R2.H * R3.L (IS);
[all...] |
| c_dsp32mac_pair_a0_i.s | 19 A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS);
21 A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS);
24 A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS);
26 A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS);
50 A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS);
52 A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS);
54 A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS);
56 A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS);
79 A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS);
81 A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS);
[all...] |
| c_dsp32mac_pair_a1_i.s | 19 R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS);
21 R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS);
23 R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS);
25 R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS);
48 R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS);
50 R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
52 R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS);
54 R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS);
77 R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS);
79 R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS);
[all...] |
| c_dsp32mac_pair_a1a0_i.s | 19 R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (IS);
22 R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (IS);
25 R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (IS);
28 R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (IS);
54 R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (IS);
57 R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ) (IS);
61 R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (IS);
64 R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (IS);
90 R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (IS);
93 R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (IS);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_dsp32mult_dr_m_i.s | 16 R4.L = R0.H * R0.L (IS);
17 R5.H = R0.L * R1.L (IS);
18 R6.L = R1.L * R0.H (IS);
19 R7.L = R1.L * R1.L (IS);
20 R0.H = R0.L * R0.L (IS);
21 R1.L = R0.L * R1.L (IS);
22 R2.L = R1.H * R0.L (IS);
23 R3.H = R1.L * R1.L (IS);
41 R5.H = R2.L * R2.L (IS);
42 R6.L = R2.L * R3.H (IS);
[all...] |
| c_dsp32mult_dr_i.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS);
17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS);
18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS);
19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS);
20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS);
21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS);
22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS);
23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS);
41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS);
42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS);
[all...] |
| c_dsp32mult_pair_m_i.s | 16 R0 = R0.L * R0.L (IS);
17 R2 = R0.L * R1.H (IS);
18 R4 = R1.H * R1.H (IS);
19 R6 = R0.L * R0.L (IS);
37 R0 = R2.L * R2.L (IS);
38 R2 = R2.L * R3.H (IS);
39 R4 = R3.H * R2.H (IS);
40 R6 = R2.L * R3.L (IS);
58 R0 = R4.L * R4.L (IS);
59 R2 = R4.L * R5.H (IS);
[all...] |
| c_dsp32mult_pair_i.s | 16 R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS);
17 R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS);
18 R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS);
19 R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS);
37 R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS);
38 R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS);
39 R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS);
40 R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS);
58 R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS);
59 R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS);
[all...] |
| c_dsp32mac_dr_a0_i.s | 22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS);
24 A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS);
26 A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS);
28 A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS);
48 R0.L = ( A0 -= R1.L * R0.L ) (IS);
50 R2.L = ( A0 += R2.L * R3.H ) (IS);
52 R4.L = ( A0 = R4.H * R5.L ) (IS);
54 R6.L = ( A0 -= R6.H * R7.H ) (IS);
74 R0.L = ( A0 = R1.L * R0.L ) (IS);
76 R2.L = ( A0 -= R2.H * R3.L ) (IS);
[all...] |
| c_dsp32mac_dr_a1_i.s | 21 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS);
23 R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
25 R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS);
27 R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS);
47 R0.H = ( A1 = R1.L * R0.L ) (IS);
49 R2.H = ( A1 += R2.L * R3.H ) (IS);
51 R4.H = ( A1 = R4.H * R5.L ) (IS);
53 R6.H = ( A1 = R6.H * R7.H ) (IS);
73 R0.H = A1 , A0 = R1.L * R0.L (IS);
75 R2.H = A1 , A0 = R2.H * R3.L (IS);
[all...] |
| c_dsp32mac_pair_a0_i.s | 19 A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS);
21 A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS);
24 A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS);
26 A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS);
50 A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS);
52 A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS);
54 A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS);
56 A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS);
79 A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS);
81 A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS);
[all...] |
| c_dsp32mac_pair_a1_i.s | 19 R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS);
21 R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS);
23 R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS);
25 R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS);
48 R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS);
50 R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
52 R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS);
54 R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS);
77 R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS);
79 R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| SchedulerRegistry.h | 63 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
68 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
75 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
82 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
87 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
93 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
97 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
102 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 45 const InstrStage *IS = ItinData->beginStage(idx);
49 for (; IS != E; ++IS) {
50 unsigned StageDepth = CurCycle + IS->getCycles();
52 CurCycle += IS->getNextCycles();
69 // If MaxLookAhead is not set above, then we are not enabled.
129 for (const InstrStage *IS = ItinData->beginStage(idx),
130 *E = ItinData->endStage(idx); IS != E; ++IS) {
132 // stage is occupied. FIXME it would be more accurate to find th
[all...] |
| TargetSubtargetInfo.cpp | 21 const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| Scheduler.cpp | 33 dbgs() << "[SCHEDULER]: WaitSet size is: " << WaitSet.size() << '\n';
34 dbgs() << "[SCHEDULER]: ReadySet size is: " << ReadySet.size() << '\n';
35 dbgs() << "[SCHEDULER]: IssuedSet size is: " << IssuedSet.size() << '\n';
73 Instruction *IS = IR.getInstruction();
74 const InstrDesc &D = IS->getDesc();
77 // into a vector. That vector is then used to notify the listener.
82 IS->execute(IR.getSourceIndex());
84 IS->computeCriticalRegDep();
86 if (IS->isMemOp()) {
88 const MemoryGroup &Group = LSU.getGroup(IS->getLSUTokenID())
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/fuzzer/ |
| FuzzerMerge.h | 5 // This file is distributed under the University of Illinois Open Source
64 bool Parse(std::istream &IS, bool ParseCoverage);
66 void ParseOrExit(std::istream &IS, bool ParseCoverage);
68 Set<uint32_t> ParseSummary(std::istream &IS);
|
| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/Native/ |
| NativeExeSymbol.cpp | 68 auto IS = Session.getPDBFile().getPDBInfoStream();
69 if (IS)
70 return IS->getAge();
71 consumeError(IS.takeError());
80 auto IS = Session.getPDBFile().getPDBInfoStream();
81 if (IS)
82 return IS->getGuid();
83 consumeError(IS.takeError());
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| DispatchStage.cpp | 12 /// The DispatchStage is responsible for updating instruction dependencies
14 /// is ready to be scheduled for execution.
80 Instruction &IS = *IR.getInstruction();
81 const InstrDesc &Desc = IS.getDesc();
82 const unsigned NumMicroOps = IS.getNumMicroOps();
97 // Check if this is an optimizable reg-reg move or an XCHG-like instruction.
98 if (IS.isOptimizableMove())
99 if (PRF.tryEliminateMoveOrSwap(IS.getDefs(), IS.getUses()))
100 IS.setEliminated()
[all...] |
| InOrderIssueStage.cpp | 113 // Try again in the next cycle until the value is known
176 static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS,
180 assert(!IS.isEliminated());
182 for (ReadState &RS : IS.getUses())
185 for (WriteState &WS : IS.getDefs())
223 Instruction &IS = *IR.getInstruction();
225 const InstrDesc &Desc = IS.getDesc();
235 IS.dispatch(RCUTokenID);
238 addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs);
240 unsigned NumMicroOps = IS.getNumMicroOps()
[all...] |
