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    Searched refs:LinkLevel (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 584 table->LinkLevel[i].PcieGenSpeed =
586 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
588 table->LinkLevel[i].EnabledForActivity = 1;
589 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
590 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
591 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
2116 table->LinkLevel[i - 1].BifSclkDfs =
amdgpu_fiji_smumgr.c 844 table->LinkLevel[i].PcieGenSpeed =
846 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
848 table->LinkLevel[i].EnabledForActivity = 1;
849 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
850 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
851 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
amdgpu_iceland_smumgr.c 778 table->LinkLevel[i].PcieGenSpeed =
780 table->LinkLevel[i].PcieLaneCount =
782 table->LinkLevel[i].EnabledForActivity =
784 table->LinkLevel[i].SPC =
786 table->LinkLevel[i].DownThreshold =
788 table->LinkLevel[i].UpThreshold =
amdgpu_polaris10_smumgr.c 782 table->LinkLevel[i].PcieGenSpeed =
784 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
786 table->LinkLevel[i].EnabledForActivity = 1;
787 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
788 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
789 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
2000 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
amdgpu_tonga_smumgr.c 521 table->LinkLevel[i].PcieGenSpeed =
523 table->LinkLevel[i].PcieLaneCount =
525 table->LinkLevel[i].EnabledForActivity =
527 table->LinkLevel[i].SPC =
529 table->LinkLevel[i].DownThreshold =
531 table->LinkLevel[i].UpThreshold =
amdgpu_ci_smumgr.c 1009 table->LinkLevel[i].PcieGenSpeed =
1011 table->LinkLevel[i].PcieLaneCount =
1013 table->LinkLevel[i].EnabledForActivity = 1;
1014 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
1015 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu71_discrete.h 275 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK];
smu7_discrete.h 328 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
smu72_discrete.h 270 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
smu73_discrete.h 254 SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK];
smu74_discrete.h 286 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
smu75_discrete.h 292 SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_discrete.h 327 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
radeon_ci_dpm.c 2640 table->LinkLevel[i].PcieGenSpeed =
2642 table->LinkLevel[i].PcieLaneCount =
2644 table->LinkLevel[i].EnabledForActivity = 1;
2645 table->LinkLevel[i].DownT = cpu_to_be32(5);
2646 table->LinkLevel[i].UpT = cpu_to_be32(30);

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