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    Searched refs:MESON_CLK_PLL_REG (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxbb_clkc.c 96 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
97 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
98 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
100 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
101 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
110 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
111 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
112 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
113 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
114 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l *
    [all...]
meson8b_clkc.c 185 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
186 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
187 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
189 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
190 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
240 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
241 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
242 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
243 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
244 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l *
    [all...]
mesong12_clkc.c 187 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(28)), /* enable */ \
188 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(7,0)), /* m */ \
189 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(14,10)),/* n */ \
190 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL1, __BITS(16,0)), /* frac */ \
191 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(31)), /* l */ \
192 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(29)), /* reset */ \
205 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(28)), /* enable */ \
206 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(7,0)), /* m */ \
207 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(14,10)),/* n */ \
209 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(31)), /* l */
    [all...]
meson_clk.h 232 struct meson_clk_pll_reg { struct
237 #define MESON_CLK_PLL_REG(_reg, _mask) \
239 #define MESON_CLK_PLL_REG_INVALID MESON_CLK_PLL_REG(0,0)
242 struct meson_clk_pll_reg enable;
243 struct meson_clk_pll_reg m;
244 struct meson_clk_pll_reg n;
245 struct meson_clk_pll_reg frac;
246 struct meson_clk_pll_reg l;
247 struct meson_clk_pll_reg reset;
302 struct meson_clk_pll_reg sdm
    [all...]

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