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    Searched refs:MemoryLevel (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c 1312 uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
1314 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1323 &(smu_data->smc_state_table.MemoryLevel[i]));
1328 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1334 smu_data->smc_state_table.MemoryLevel[1].MinVddci =
1335 smu_data->smc_state_table.MemoryLevel[0].MinVddci;
1336 smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
1337 smu_data->smc_state_table.MemoryLevel[0].MinMvdd;
1339 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1340 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel)
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amdgpu_iceland_smumgr.c 1359 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1361 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1370 &(smu_data->smc_state_table.MemoryLevel[i]));
1377 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1384 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1385 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1390 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
amdgpu_tonga_smumgr.c 1102 offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
1107 smu_data->smc_state_table.MemoryLevel;
1119 &(smu_data->smc_state_table.MemoryLevel[i]));
1125 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1132 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1133 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1138 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1247 smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
3163 offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
3165 smu_data->smc_state_table.MemoryLevel;
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amdgpu_fiji_smumgr.c 1234 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
1238 smu_data->smc_state_table.MemoryLevel;
2564 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2566 smu_data->smc_state_table.MemoryLevel;
amdgpu_polaris10_smumgr.c 159 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1137 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1141 smu_data->smc_state_table.MemoryLevel;
2480 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2482 smu_data->smc_state_table.MemoryLevel;
amdgpu_vegam_smumgr.c 1044 offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1048 smu_data->smc_state_table.MemoryLevel;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu71_discrete.h 213 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
274 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY];
smu7_discrete.h 327 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY];
smu72_discrete.h 269 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
smu73_discrete.h 253 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY];
smu74_discrete.h 285 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
smu75_discrete.h 291 SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_discrete.h 326 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY];
radeon_ci_dpm.c 3334 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3337 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3347 &pi->smc_state_table.MemoryLevel[i]);
3352 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3356 pi->smc_state_table.MemoryLevel[1].MinVddc =
3357 pi->smc_state_table.MemoryLevel[0].MinVddc;
3358 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3359 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3362 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3368 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark
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