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    Searched refs:PACKET3_SET_CONFIG_REG_START (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
nvd.h 273 #define PACKET3_SET_CONFIG_REG_START 0x00002000
si_enums.h 263 #define PACKET3_SET_CONFIG_REG_START 0x00002000
soc15d.h 265 #define PACKET3_SET_CONFIG_REG_START 0x00002000
vid.h 344 #define PACKET3_SET_CONFIG_REG_START 0x00002000
cikd.h 462 #define PACKET3_SET_CONFIG_REG_START 0x00002000
amdgpu_gfx_v6_0.c 1813 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1846 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1927 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
sid.h 1848 #define PACKET3_SET_CONFIG_REG_START 0x00002000
amdgpu_gfx_v7_0.c 2317 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
amdgpu_gfx_v8_0.c 6139 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_cs.c 2330 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2332 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
3451 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3453 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
nid.h 1272 #define PACKET3_SET_CONFIG_REG_START 0x00008000
radeon_si.c 3389 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3429 PACKET3_SET_CONFIG_REG_START) >> 2));
3455 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4629 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4631 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
cikd.h 1928 #define PACKET3_SET_CONFIG_REG_START 0x00008000
sid.h 1785 #define PACKET3_SET_CONFIG_REG_START 0x00008000
evergreend.h 1668 #define PACKET3_SET_CONFIG_REG_START 0x00008000
radeon_ni.c 1447 PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_evergreen.c 2948 PACKET3_SET_CONFIG_REG_START) >> 2));

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