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    Searched refs:PcieLaneCount (Results 1 - 23 of 23) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu9_driver_if.h 239 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
smu71_discrete.h 156 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
smu7_discrete.h 214 uint8_t PcieLaneCount;
smu11_driver_if.h 455 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
smu11_driver_if_navi10.h 628 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
smu72_discrete.h 147 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
smu73_discrete.h 132 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
smu74_discrete.h 160 uint8_t PcieLaneCount;
smu75_discrete.h 170 uint8_t PcieLaneCount;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_vega20_ppt.c 1082 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1083 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1084 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1085 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1086 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1087 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1090 (lane_width == pptable->PcieLaneCount[i]) ?
3161 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
3162 pptable->PcieLaneCount[i] : pcie_width_cap);
amdgpu_navi10_ppt.c 658 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
1908 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1909 pptable->PcieLaneCount[i] : pcie_width_cap);
1919 if (pptable->PcieLaneCount[i] > pcie_width_cap)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_discrete.h 214 uint8_t PcieLaneCount;
radeon_ci_dpm.c 2642 table->LinkLevel[i].PcieLaneCount =
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/vega12/
smu9_driver_if.h 343 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega20_processpptables.c 407 pr_info("PcieLaneCount\n");
409 pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
amdgpu_vega10_hwmgr.c 1525 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1538 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
amdgpu_vega20_hwmgr.c 3377 lane_width = pptable->PcieLaneCount[i];
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 846 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
amdgpu_iceland_smumgr.c 780 table->LinkLevel[i].PcieLaneCount =
amdgpu_vegam_smumgr.c 586 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
amdgpu_ci_smumgr.c 1011 table->LinkLevel[i].PcieLaneCount =
amdgpu_polaris10_smumgr.c 784 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
amdgpu_tonga_smumgr.c 523 table->LinkLevel[i].PcieLaneCount =

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