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    Searched refs:Smio (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu71_discrete.h 43 uint8_t Smio;
250 // SMIO masks for voltage and phase controls
279 uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];
smu7_discrete.h 99 uint8_t Smio;
337 uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];
smu72_discrete.h 37 uint8_t Smio;
226 /* SMIO masks for voltage and phase controls */
279 uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
smu73_discrete.h 35 uint8_t Smio;
220 // SMIO masks for voltage and phase controls
263 uint32_t Smio [SMU73_MAX_ENTRIES_SMIO];
smu74_discrete.h 57 uint8_t Smio;
297 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
smu75_discrete.h 55 uint8_t Smio;
303 uint32_t Smio [SMU75_MAX_ENTRIES_SMIO];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_discrete.h 99 uint8_t Smio;
336 uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];
radeon_ci_dpm.c 2237 table->VddcLevel[count].Smio |=
2240 table->VddcLevel[count].Smio = 0;
2260 table->VddciLevel[count].Smio |=
2263 table->VddciLevel[count].Smio = 0;
2283 table->MvddLevel[count].Smio |=
2286 table->MvddLevel[count].Smio = 0;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c 860 table->VddcLevel[count].Smio = (uint8_t) count;
861 table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low;
864 table->VddcLevel[count].Smio = 0;
888 table->VddciLevel[count].Smio = (uint8_t) count;
889 table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low;
892 table->VddciLevel[count].Smio = 0;
916 table->MvddLevel[count].Smio = (uint8_t) count;
917 table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low;
920 table->MvddLevel[count].Smio = 0;
973 /* used in SMIO Mode. not implemented for now. this is backup only for CI. *
    [all...]
amdgpu_iceland_smumgr.c 638 table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
640 table->VddcLevel[count].Smio = 0;
663 table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
665 table->VddciLevel[count].Smio |= 0;
688 table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
690 table->MvddLevel[count].Smio |= 0;
742 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
amdgpu_vegam_smumgr.c 465 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
466 table->SmioTable2.Pattern[level].Smio =
468 table->Smio[level] |=
493 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
495 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
2121 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
amdgpu_polaris10_smumgr.c 664 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
665 table->SmioTable2.Pattern[level].Smio =
667 table->Smio[level] |=
692 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
694 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
2004 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
amdgpu_tonga_smumgr.c 355 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
356 table->SmioTable1.Pattern[count].Smio =
358 table->Smio[count] |=
382 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
383 table->SmioTable2.Pattern[count].Smio =
385 table->Smio[count] |=
2428 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i])
    [all...]
amdgpu_fiji_smumgr.c 2098 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

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