| /src/sys/arch/mips/cavium/dev/ |
| octeon_powreg.h | 38 #define POW_PP_GRP_MSK(core) (UINT64_C(0x0001670000000000) + (core) * 8)
39 #define POW_WQ_INT_THR0 UINT64_C(0x0001670000000080)
40 #define POW_WQ_INT_THR1 UINT64_C(0x0001670000000088)
41 #define POW_WQ_INT_THR2 UINT64_C(0x0001670000000090)
42 #define POW_WQ_INT_THR3 UINT64_C(0x0001670000000098)
43 #define POW_WQ_INT_THR4 UINT64_C(0x00016700000000a0)
44 #define POW_WQ_INT_THR5 UINT64_C(0x00016700000000a8)
45 #define POW_WQ_INT_THR6 UINT64_C(0x00016700000000b0)
46 #define POW_WQ_INT_THR7 UINT64_C(0x00016700000000b8)
47 #define POW_WQ_INT_THR8 UINT64_C(0x00016700000000c0
[all...] |
| octeon_npireg.h | 79 #define NPI_RSL_INT_BLOCKS_XXX_63_31 UINT64_C(0xffffffff80000000)
80 #define NPI_RSL_INT_BLOCKS_IOB UINT64_C(0x0000000040000000)
81 #define NPI_RSL_INT_BLOCKS_XXX_29_23 UINT64_C(0x000000003f800000)
82 #define NPI_RSL_INT_BLOCKS_ASX0 UINT64_C(0x0000000000400000)
83 #define NPI_RSL_INT_BLOCKS_XXX_21 UINT64_C(0x0000000000200000)
84 #define NPI_RSL_INT_BLOCKS_PIP UINT64_C(0x0000000000100000)
85 #define NPI_RSL_INT_BLOCKS_XXX_19_18 UINT64_C(0x00000000000c0000)
86 #define NPI_RSL_INT_BLOCKS_LMC UINT64_C(0x0000000000020000)
87 #define NPI_RSL_INT_BLOCKS_L2C UINT64_C(0x0000000000010000)
88 #define NPI_RSL_INT_BLOCKS_XXX_15_13 UINT64_C(0x000000000000e000
[all...] |
| octeon_corereg.h | 40 #define CP0_CACHEERRI_XXX_63_55 UINT64_C(0xff80000000000000)
41 #define CP0_CACHEERRI_BADCOLF UINT64_C(0x007f000000000000)
42 #define CP0_CACHEERRI_XXX_47 UINT64_C(0x0000800000000000)
43 #define CP0_CACHEERRI_BADCOL UINT64_C(0x00007f0000000000)
44 #define CP0_CACHEERRI_XXX_39_37 UINT64_C(0x000000e000000000)
45 #define CP0_CACHEERRI_LRUFAIL UINT64_C(0x0000001000000000)
46 #define CP0_CACHEERRI_AESFAIL UINT64_C(0x0000000800000000)
47 #define CP0_CACHEERRI_HSHFAIL UINT64_C(0x0000000400000000)
48 #define CP0_CACHEERRI_BHTBROKE UINT64_C(0x0000000200000000)
49 #define CP0_CACHEERRI_ICBROKE UINT64_C(0x0000000100000000
[all...] |
| octeon_pkoreg.h | 106 #define PKO_REG_FLAGS_63_7 UINT64_C(0xfffffffffffffff0)
107 #define PKO_REG_FLAGS_RESET UINT64_C(0x0000000000000008)
108 #define PKO_REG_FLAGS_STORE_BE UINT64_C(0x0000000000000004)
109 #define PKO_REG_FLAGS_ENA_DWB UINT64_C(0x0000000000000002)
110 #define PKO_REG_FLAGS_ENA_PKO UINT64_C(0x0000000000000001)
115 #define PKO_REG_READ_IDX_63_16 UINT64_C(0xffffffffffff0000)
116 #define PKO_REG_READ_IDX_INC UINT64_C(0x000000000000ff00)
117 #define PKO_REG_READ_IDX_IDX UINT64_C(0x00000000000000ff)
122 #define PKO_REG_CMD_BUF_63_23 UINT64_C(0xffffffffff800000)
123 #define PKO_REG_CMD_BUF_POOL UINT64_C(0x0000000000700000
[all...] |
| octeon_gmxreg.h | 126 #define RXN_INT_REG_XXX_63_19 UINT64_C(0xfffffffffff80000)
127 #define RXN_INT_REG_PHY_DUPX UINT64_C(0x0000000000040000)
128 #define RXN_INT_REG_PHY_SPD UINT64_C(0x0000000000020000)
129 #define RXN_INT_REG_PHY_LINK UINT64_C(0x0000000000010000)
130 #define RXN_INT_REG_IFGERR UINT64_C(0x0000000000008000)
131 #define RXN_INT_REG_COLDET UINT64_C(0x0000000000004000)
132 #define RXN_INT_REG_FALERR UINT64_C(0x0000000000002000)
133 #define RXN_INT_REG_RSVERR UINT64_C(0x0000000000001000)
134 #define RXN_INT_REG_PCTERR UINT64_C(0x0000000000000800)
135 #define RXN_INT_REG_OVRERR UINT64_C(0x0000000000000400
[all...] |
| octeon_usbnreg.h | 65 #define USBN_INT_XXX_63_38 UINT64_C(0xffffffc000000000)
66 #define USBN_INT_ND4O_DPF UINT64_C(0x0000002000000000)
67 #define USBN_INT_ND4O_DPE UINT64_C(0x0000001000000000)
68 #define USBN_INT_ND4O_RPF UINT64_C(0x0000000800000000)
69 #define USBN_INT_ND4O_RPE UINT64_C(0x0000000400000000)
70 #define USBN_INT_LTL_F_PF UINT64_C(0x0000000200000000)
71 #define USBN_INT_LTL_F_PE UINT64_C(0x0000000100000000)
72 #define USBN_INT_U2N_C_PE UINT64_C(0x0000000080000000)
73 #define USBN_INT_U2N_C_PF UINT64_C(0x0000000040000000)
74 #define USBN_INT_U2N_D_PF UINT64_C(0x0000000020000000
[all...] |
| octeon_ipdreg.h | 143 #define IPD_WQE_WORD2_RAW_BUFS UINT64_C(0xff00000000000000)
144 #define IPD_WQE_WORD2_RAW_WORD UINT64_C(0x00ffffffffffffff)
147 #define IPD_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000)
148 #define IPD_WQE_WORD2_IP_IPOFF UINT64_C(0x00ff000000000000)
149 #define IPD_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000)
150 #define IPD_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000)
151 #define IPD_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000)
152 #define IPD_WQE_WORD2_IP_VC UINT64_C(0x0000100000000000)
153 #define IPD_WQE_WORD2_IP_VLANID UINT64_C(0x00000fff00000000)
154 #define IPD_WQE_WORD2_IP_31_20 UINT64_C(0x00000000fff00000
[all...] |
| octeon_rnmreg.h | 42 #define RNM_CTL_STATUS UINT64_C(0x0001180040000000)
43 #define RNM_BIST_STATUS UINT64_C(0x0001180040000008)
47 #define RNM_CTL_STATUS_XXX_63_5 UINT64_C(0xfffffffffffffe00)
48 #define RNM_CTL_STATUS_ENT_SEL_MASK UINT64_C(0x00000000000001e0)
49 #define RNM_CTL_STATUS_EXP_ENT UINT64_C(0x0000000000000010)
50 #define RNM_CTL_STATUS_RNG_RST UINT64_C(0x0000000000000008)
51 #define RNM_CTL_STATUS_RNM_RST UINT64_C(0x0000000000000004)
52 #define RNM_CTL_STATUS_RNG_EN UINT64_C(0x0000000000000002)
53 #define RNM_CTL_STATUS_ENT_EN UINT64_C(0x0000000000000001)
55 #define RNM_BIST_STATUS_XXX_63_2 UINT64_C(0xfffffffffffffffc
[all...] |
| octeon_twsireg.h | 45 #define MIO_TWS_SW_TWSI_V UINT64_C(0x8000000000000000)
46 #define MIO_TWS_SW_TWSI_SLONLY UINT64_C(0x4000000000000000)
47 #define MIO_TWS_SW_TWSI_EIA UINT64_C(0x2000000000000000)
48 #define MIO_TWS_SW_TWSI_OP UINT64_C(0x1e00000000000000)
55 #define MIO_TWS_SW_TWSI_R UINT64_C(0x0100000000000000)
56 #define MIO_TWS_SW_TWSI_SOVR UINT64_C(0x0080000000000000)
57 #define MIO_TWS_SW_TWSI_SIZE UINT64_C(0x0070000000000000)
58 #define MIO_TWS_SW_TWSI_SCR UINT64_C(0x000c000000000000)
59 #define MIO_TWS_SW_TWSI_A UINT64_C(0x0003ff0000000000)
60 #define MIO_TWS_SW_TWSI_IA UINT64_C(0x000000f800000000
[all...] |
| octeon_smireg.h | 48 #define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000)
49 #define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000)
52 #define SMI_CMD_15_13 UINT64_C(0x000000000000e000)
53 #define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00)
54 #define SMI_CMD_7_5 UINT64_C(0x00000000000000e0)
55 #define SMI_CMD_REG_ADR UINT64_C(0x000000000000001f)
58 #define SMI_WR_DAT_63_18 UINT64_C(0xfffffffffffc0000)
59 #define SMI_WR_DAT_PENDING UINT64_C(0x0000000000020000)
60 #define SMI_WR_DAT_VAL UINT64_C(0x0000000000010000)
61 #define SMI_WR_DAT_DAT UINT64_C(0x000000000000ffff
[all...] |
| octeon_fpareg.h | 65 #define FPA_INT_SUM_XXX_63_28 UINT64_C(0xfffffffff0000000)
66 #define FPA_INT_SUM_Q7_PERR UINT64_C(0x0000000008000000)
67 #define FPA_INT_SUM_Q7_COFF UINT64_C(0x0000000004000000)
68 #define FPA_INT_SUM_Q7_UND UINT64_C(0x0000000002000000)
69 #define FPA_INT_SUM_Q6_PERR UINT64_C(0x0000000001000000)
70 #define FPA_INT_SUM_Q6_COFF UINT64_C(0x0000000000800000)
71 #define FPA_INT_SUM_Q6_UND UINT64_C(0x0000000000400000)
72 #define FPA_INT_SUM_Q5_PERR UINT64_C(0x0000000000200000)
73 #define FPA_INT_SUM_Q5_COFF UINT64_C(0x0000000000100000)
74 #define FPA_INT_SUM_Q5_UND UINT64_C(0x0000000000080000
[all...] |
| octeon_mpireg.h | 49 #define MPI_CFG_XXX_63_29 UINT64_C(0xffffffffe0000000)
50 #define MPI_CFG_CLKDIV UINT64_C(0x000000001fff0000)
51 #define MPI_CFG_XXX_15_12 UINT64_C(0x000000000000f000)
52 #define MPI_CFG_CSLATE UINT64_C(0x0000000000000800)
53 #define MPI_CFG_TRITX UINT64_C(0x0000000000000400)
54 #define MPI_CFG_IDLECLKS UINT64_C(0x0000000000000300)
55 #define MPI_CFG_CSHI UINT64_C(0x0000000000000080)
56 #define MPI_CFG_CSENA UINT64_C(0x0000000000000040)
57 #define MPI_CFG_INT_ENA UINT64_C(0x0000000000000020)
58 #define MPI_CFG_LSBFIRST UINT64_C(0x0000000000000010
[all...] |
| octeon_ciureg.h | 38 #define CIU_INT0_SUM0 UINT64_C(0x0001070000000000)
39 #define CIU_INT1_SUM0 UINT64_C(0x0001070000000008)
40 #define CIU_INT2_SUM0 UINT64_C(0x0001070000000010)
41 #define CIU_INT3_SUM0 UINT64_C(0x0001070000000018)
44 #define CIU_INT32_SUM0 UINT64_C(0x0001070000000100)
45 #define CIU_INT_SUM1 UINT64_C(0x0001070000000108)
46 #define CIU_INT0_EN0 UINT64_C(0x0001070000000200)
47 #define CIU_INT1_EN0 UINT64_C(0x0001070000000210)
48 #define CIU_INT2_EN0 UINT64_C(0x0001070000000220)
49 #define CIU_INT3_EN0 UINT64_C(0x0001070000000230
[all...] |
| octeon_pipreg.h | 213 #define PIP_BIST_STATUS_63_13 UINT64_C(0xfffffffffffc0000)
214 #define PIP_BIST_STATUS_BIST UINT64_C(0x000000000003ffff)
219 #define PIP_INT_REG_63_9 UINT64_C(0xfffffffffffffe00)
220 #define PIP_INT_REG_BEPERR UINT64_C(0x0000000000000100)
221 #define PIP_INT_REG_FEPERR UINT64_C(0x0000000000000080)
222 #define PIP_INT_REG_6 UINT64_C(0x0000000000000040)
223 #define PIP_INT_REG_SKPRUNT UINT64_C(0x0000000000000020)
224 #define PIP_INT_REG_BADTAG UINT64_C(0x0000000000000010)
225 #define PIP_INT_REG_PRTNXA UINT64_C(0x0000000000000008)
232 #define PIP_INT_EN_63_9 UINT64_C(0xfffffffffffffe00
[all...] |
| octeon_bootbusreg.h | 65 #define MIO_BOOT_REG_CFGN_XXX_63_37 UINT64_C(0xffffffe000000000)
66 #define MIO_BOOT_REG_CFGN_SAM UINT64_C(0x0000001000000000)
67 #define MIO_BOOT_REG_CFGN_WE_EXT UINT64_C(0x0000000c00000000)
68 #define MIO_BOOT_REG_CFGN_OE_EXT UINT64_C(0x0000000300000000)
69 #define MIO_BOOT_REG_CFGN_EN UINT64_C(0x0000000080000000)
70 #define MIO_BOOT_REG_CFGN_OR UINT64_C(0x0000000040000000)
71 #define MIO_BOOT_REG_CFGN_ALE UINT64_C(0x0000000020000000)
72 #define MIO_BOOT_REG_CFGN_WIDTH UINT64_C(0x0000000010000000)
73 #define MIO_BOOT_REG_CFGN_SIZE UINT64_C(0x000000000fff0000)
74 #define MIO_BOOT_REG_CFGN_BASE UINT64_C(0x000000000000ffff
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/ |
| floatsitf_test.c | 43 if (test__floatsitf(0x80000000, UINT64_C(0xc01e000000000000), UINT64_C(0x0)))
45 if (test__floatsitf(0x7fffffff, UINT64_C(0x401dfffffffc0000), UINT64_C(0x0)))
47 if (test__floatsitf(0, UINT64_C(0x0), UINT64_C(0x0)))
49 if (test__floatsitf(0xffffffff, UINT64_C(0xbfff000000000000), UINT64_C(0x0)))
51 if (test__floatsitf(0x12345678, UINT64_C(0x401b234567800000), UINT64_C(0x0))
[all...] |
| floatditf_test.c | 45 if (test__floatditf(0x7fffffffffffffff, UINT64_C(0x403dffffffffffff), UINT64_C(0xfffc000000000000)))
47 if (test__floatditf(0x123456789abcdef1, UINT64_C(0x403b23456789abcd), UINT64_C(0xef10000000000000)))
49 if (test__floatditf(0x2, UINT64_C(0x4000000000000000), UINT64_C(0x0)))
51 if (test__floatditf(0x1, UINT64_C(0x3fff000000000000), UINT64_C(0x0)))
53 if (test__floatditf(0x0, UINT64_C(0x0), UINT64_C(0x0))
[all...] |
| floatunsitf_test.c | 42 if (test__floatunsitf(0x7fffffff, UINT64_C(0x401dfffffffc0000), UINT64_C(0x0)))
44 if (test__floatunsitf(0, UINT64_C(0x0), UINT64_C(0x0)))
46 if (test__floatunsitf(0xffffffff, UINT64_C(0x401efffffffe0000), UINT64_C(0x0)))
48 if (test__floatunsitf(0x12345678, UINT64_C(0x401b234567800000), UINT64_C(0x0)))
|
| divtf3_test.c | 48 UINT64_C(0x7fff800000000000),
49 UINT64_C(0x0)))
52 if (test__divtf3(makeNaN128(UINT64_C(0x800030000000)),
54 UINT64_C(0x7fff800000000000),
55 UINT64_C(0x0)))
60 UINT64_C(0x7fff000000000000),
61 UINT64_C(0x0)))
66 UINT64_C(0x4004b0b72924d407),
67 UINT64_C(0x0717e84356c6eba2)))
71 UINT64_C(0x3fd5b2af3f828c9b)
[all...] |
| extenddftf2_test.c | 44 UINT64_C(0x7fff800000000000),
45 UINT64_C(0x0)))
48 if (test__extenddftf2(makeNaN64(UINT64_C(0x7100000000000)),
49 UINT64_C(0x7fff710000000000),
50 UINT64_C(0x0)))
54 UINT64_C(0x7fff000000000000),
55 UINT64_C(0x0)))
58 if (test__extenddftf2(0.0, UINT64_C(0x0), UINT64_C(0x0)))
62 UINT64_C(0x400423456789abcd)
[all...] |
| multf3_test.c | 47 UINT64_C(0x7fff800000000000),
48 UINT64_C(0x0)))
51 if (test__multf3(makeNaN128(UINT64_C(0x800030000000)),
53 UINT64_C(0x7fff800000000000),
54 UINT64_C(0x0)))
59 UINT64_C(0x7fff000000000000),
60 UINT64_C(0x0)))
65 UINT64_C(0x400423e7f9e3c9fc),
66 UINT64_C(0xd906c2c2a85777c4)))
70 UINT64_C(0x3fc52a163c6223fc)
[all...] |
| extendsftf2_test.c | 45 UINT64_C(0x7fff800000000000),
46 UINT64_C(0x0)))
50 UINT64_C(0x7fff820000000000),
51 UINT64_C(0x0)))
55 UINT64_C(0x7fff000000000000),
56 UINT64_C(0x0)))
59 if (test__extendsftf2(0.0f, UINT64_C(0x0), UINT64_C(0x0)))
63 UINT64_C(0x4004234560000000),
64 UINT64_C(0x0))
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/test/Unit/ppc/ |
| floatunditf_test.h | 8 { UINT64_C(0x0000000000000061), 0x1.84p+6, 0x0p+0 },
9 { UINT64_C(0x0000000000000062), 0x1.88p+6, 0x0p+0 },
10 { UINT64_C(0x0000000000000403), 0x1.00cp+10, 0x0p+0 },
11 { UINT64_C(0x000000000000040a), 0x1.028p+10, 0x0p+0 },
12 { UINT64_C(0x000000000000040c), 0x1.03p+10, 0x0p+0 },
13 { UINT64_C(0x000000000000040e), 0x1.038p+10, 0x0p+0 },
14 { UINT64_C(0x0000000000000418), 0x1.06p+10, 0x0p+0 },
15 { UINT64_C(0x000000000000041a), 0x1.068p+10, 0x0p+0 },
16 { UINT64_C(0x0000000000000504), 0x1.41p+10, 0x0p+0 },
17 { UINT64_C(0x0000000000000506), 0x1.418p+10, 0x0p+0 }
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/ppc/ |
| floatunditf_test.h | 8 { UINT64_C(0x0000000000000061), 0x1.84p+6, 0x0p+0 },
9 { UINT64_C(0x0000000000000062), 0x1.88p+6, 0x0p+0 },
10 { UINT64_C(0x0000000000000403), 0x1.00cp+10, 0x0p+0 },
11 { UINT64_C(0x000000000000040a), 0x1.028p+10, 0x0p+0 },
12 { UINT64_C(0x000000000000040c), 0x1.03p+10, 0x0p+0 },
13 { UINT64_C(0x000000000000040e), 0x1.038p+10, 0x0p+0 },
14 { UINT64_C(0x0000000000000418), 0x1.06p+10, 0x0p+0 },
15 { UINT64_C(0x000000000000041a), 0x1.068p+10, 0x0p+0 },
16 { UINT64_C(0x0000000000000504), 0x1.41p+10, 0x0p+0 },
17 { UINT64_C(0x0000000000000506), 0x1.418p+10, 0x0p+0 }
[all...] |
| /src/sys/arch/mips/cavium/ |
| octeonreg.h | 41 #define OCTEON_CVMSEG_LM UINT64_C(0xffffffffffff8000)
42 #define OCTEON_CVMSEG_IO UINT64_C(0xffffffffffffa000)
44 #define OCTEON_IOBDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa200)
45 #define OCTEON_IOBDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb200)
46 #define OCTEON_LMTDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa400)
47 #define OCTEON_LMTDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb400)
86 #define MIO_RST_BOOT UINT64_C(0x1180000001600)
92 #define MIO_FUS_PDF UINT64_C(0x1180000001428)
95 #define RST_BOOT UINT64_C(0x1180006001600)
98 #define RST_DELAY UINT64_C(0x1180006001608
[all...] |
