| /src/sys/arch/mips/alchemy/dev/ |
| aupcireg.h | 38 #define AUPCI_CMEM_HC (1UL<<31) /* host config */
39 #define AUPCI_CMEM_E (1UL<<28) /* cmem enable */
43 #define AUPCI_CONFIG_ERD (1UL<<27) /* error direction */
44 #define AUPCI_CONFIG_ET (1UL<<26) /* error target */
45 #define AUPCI_CONFIG_EF (1UL<<25) /* fatal error */
46 #define AUPCI_CONFIG_EP (1UL<<24) /* parity error */
47 #define AUPCI_CONFIG_EM (1UL<<23) /* multiple errors */
48 #define AUPCI_CONfIG_BM (1UL<<22) /* bad master */
49 #define AUPCI_CONFIG_PD (1UL<<20) /* PCI disable */
50 #define AUPCI_CONFIG_BME (1UL<<19) /* byte mask enable *
[all...] |
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/ |
| nmi.h | 38 #define XEN_NMIREASON_io_error (1UL << _XEN_NMIREASON_io_error)
41 #define XEN_NMIREASON_pci_serr (1UL << _XEN_NMIREASON_pci_serr)
45 #define XEN_NMIREASON_parity_error (1UL << _XEN_NMIREASON_parity_error)
49 #define XEN_NMIREASON_unknown (1UL << _XEN_NMIREASON_unknown)
|
| xencomm.h | 33 #define XENCOMM_INVALID (~0UL)
|
| /src/sys/arch/alpha/pci/ |
| irongatereg.h | 66 #define IRONGATE_KSEG_BIAS 0x0100##0000##0000UL
68 #define IRONGATE_MEM_BASE (IRONGATE_KSEG_BIAS | 0x0000##0000##0000UL)
69 #define IRONGATE_IACK_BASE (IRONGATE_KSEG_BIAS | 0x0001##f800##0000UL)
70 #define IRONGATE_IO_BASE (IRONGATE_KSEG_BIAS | 0x0001##fc00##0000UL)
71 #define IRONGATE_SELF_BASE (IRONGATE_KSEG_BIAS | 0x0001##fe00##0000UL)
|
| tsreg.h | 54 #define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
82 #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
88 #define TS_C_MTR 0x101##a000##0040UL
90 #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
103 #define TS_C_AAR0 0x101##a000##0100UL
104 #define TS_C_AAR1 0x101##a000##0140UL
105 #define TS_C_AAR2 0x101##a000##0180UL
111 #define TS_C_DIM0 0x101##a000##0200UL
112 #define TS_C_DIM1 0x101##a000##0240UL
113 #define TS_C_DIR0 0x101##a000##0280UL
[all...] |
| ttwoga.c | 89 #define GIGABYTE (1024UL * 1024UL * 1024UL)
90 #define MEGABYTE (1024UL * 1024UL)
94 { T2_PCI0_SIO_BASE, 256UL * MEGABYTE, 8UL * MEGABYTE,
95 T2_PCI0_SMEM_BASE, 4UL * GIGABYTE, 128UL * MEGABYTE,
96 T2_PCI0_DMEM_BASE, 1UL * GIGABYTE, 1UL * GIGABYTE
[all...] |
| /src/sys/arch/or1k/include/ |
| vmparam.h | 53 #define MAXTSIZ (1UL << 26) /* 32bit max text size (64MB) */
57 #define MAXDSIZ (1UL << 30) /* max data size (1024MB) */
61 #define MAXSSIZ (1UL << 26) /* max stack size (64MB) */
65 #define DFLDSIZ (1UL << 27) /* 32bit default data size (128MB) */
69 #define DFLSSIZ (1UL << 21) /* 32bit default stack size (2MB) */
|
| param.h | 59 #define NKMEMPAGES_MAX_DEFAULT ((2048UL * 1024 * 1024) >> PAGE_SHIFT)
60 #define NKMEMPAGES_MIN_DEFAULT ((128UL * 1024 * 1024) >> PAGE_SHIFT)
|
| /src/sys/arch/sparc64/dev/ |
| schizoreg.h | 217 #define SCZ_PCICTRL_BUS_UNUS (1ULL << 63UL) /* bus unusable */
218 #define TOM_PCICTRL_DTO_ERR (1ULL << 62UL) /* pci discard timeout */
219 #define TOM_PCICTRL_DTO_INT (1ULL << 61UL) /* discard intr en */
220 #define SCZ_PCICTRL_ESLCK (1ULL << 51UL) /* error slot locked */
221 #define SCZ_PCICTRL_ERRSLOT (7ULL << 48UL) /* error slot */
222 #define SCZ_PCICTRL_TTO_ERR (1ULL << 38UL) /* pci trdy# timeout */
223 #define SCZ_PCICTRL_RTRY_ERR (1ULL << 37UL) /* pci rtry# timeout */
224 #define SCZ_PCICTRL_MMU_ERR (1ULL << 36UL) /* pci mmu error */
225 #define SCZ_PCICTRL_SBH_ERR (1ULL << 35UL) /* pci strm hole */
226 #define SCZ_PCICTRL_SERR (1ULL << 34UL) /* pci serr# sampled *
[all...] |
| /src/tests/usr.bin/xlint/lint1/ |
| platform_ilp32_c90.c | 134 2147483647UL,
138 2147483648UL,
142 4294967295UL,
146 4294967296UL,
151 9223372036854775807UL,
156 9223372036854775808UL,
161 18446744073709551615UL,
167 18446744073709551616UL,
|
| platform_ilp32_c99.c | 122 2147483647UL,
126 2147483648UL,
130 4294967295UL,
134 4294967296UL,
138 9223372036854775807UL,
142 9223372036854775808UL,
146 18446744073709551615UL,
151 18446744073709551616UL,
|
| platform_lp64_c90.c | 122 2147483647UL,
126 2147483648UL,
130 4294967295UL,
134 4294967296UL,
138 9223372036854775807UL,
142 9223372036854775808UL,
146 18446744073709551615UL,
151 18446744073709551616UL,
|
| platform_lp64_c99.c | 122 2147483647UL,
126 2147483648UL,
130 4294967295UL,
134 4294967296UL,
138 9223372036854775807UL,
142 9223372036854775808UL,
146 18446744073709551615UL,
151 18446744073709551616UL,
|
| msg_097.c | 21 unsigned long ul = 1234567UL; local in function:example
|
| /src/sys/arch/riscv/include/ |
| int_const.h | 18 #define __UINT64_C_SUFFIX__ UL
25 #define __UINTMAX_C_SUFFIX__ UL
|
| /src/sys/arch/sparc64/include/ |
| vmparam.h | 82 #define PAGE_SIZE_4M (1UL<<PAGE_SHIFT_4M)
109 #define MAXTSIZ (4UL*1024*1024*1024) /* max text size */
112 #define DFLDSIZ (128UL*1024*1024) /* initial data size limit */
115 #define MAXDSIZ (1UL<<39) /* 512GB max data size */
122 round_page((vaddr_t)(da) + (vsize_t)uimax(maxdmap,1UL*1024*1024*1024))
139 #define MAXTSIZ (2UL*1024*1024*1024) /* max text size */
145 #define MAXDSIZ (2UL*1024*1024*1024) /* max data size */
|
| /src/sys/arch/amd64/stand/prekern/ |
| pdir.h | 55 #define NBPD_L1 (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
56 #define NBPD_L2 (1UL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
57 #define NBPD_L3 (1UL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
58 #define NBPD_L4 (1UL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
|
| /src/sys/arch/alpha/include/ |
| int_const.h | 52 #define UINT64_C(c) c ## UL
57 #define UINTMAX_C(c) c ## UL
|
| /src/sys/arch/ia64/include/ |
| int_const.h | 53 #define UINT64_C(c) c ## UL
58 #define UINTMAX_C(c) c ## UL
|
| /src/tests/usr.bin/indent/ |
| lsym_word.c | 73 unsigned long ul[] = {0b00001111UL, 0x01010101UL, 02UL, 17UL}; local in function:t
90 unsigned long ul[] = {0b00001111UL, 0x01010101UL, 02UL, 17UL}; local in function:t
103 unsigned long x = 314UL;
115 unsigned long x = 314UL;
|
| /src/lib/libc/gdtoa/ |
| qnan.c | 68 #define UL (unsigned long)
88 printf("#define f_QNAN 0x%lx\n", UL c.L[0]);
92 printf("#define d_QNAN0 0x%lx\n", UL c.L[0]);
93 printf("#define d_QNAN1 0x%lx\n", UL c.L[1]);
106 printf("#define ld_QNAN%d 0x%lx\n", i, UL a.L[i]);
|
| /src/sys/arch/arm/at91/ |
| at91aicreg.h | 34 #define AIC_NIRQ 32UL /* number of vectors */
37 #define AIC_SMR(vec) (0x000UL+(vec)*4UL)/* Source Mode Registers */
38 #define AIC_SVR(vec) (0x080UL+(vec)*4UL)/* Source Vectors Regs */
|
| /src/sys/arch/i386/i386/ |
| rbus_machdep.c | 89 if (ram <= 192*1024*1024UL) {
96 rbus_min_start = 512 * 1024 * 1024UL;
99 if (ram >= 1024*1024*1024UL) {
103 rbus_min_start = 2 * 1024 * 1024 * 1024UL;
107 if (ram > 2 * 1024*1024*1024UL) {
111 rbus_min_start = 3 * 1024 * 1024 * 1024UL;
|
| /src/sys/arch/aarch64/include/ |
| pte.h | 102 #define L0_SIZE (1UL << L0_SHIFT)
103 #define L0_OFFSET (L0_SIZE - 1UL)
111 #define L1_SIZE (1UL << L1_SHIFT)
112 #define L1_OFFSET (L1_SIZE - 1UL)
120 #define L2_SIZE (1UL << L2_SHIFT)
121 #define L2_OFFSET (L2_SIZE - 1UL)
130 #define L3_SIZE (1UL << L3_SHIFT)
131 #define L3_OFFSET (L3_SIZE - 1UL)
|
| /src/sys/arch/amd64/include/ |
| int_const.h | 55 #define UINT64_C(c) c ## UL
60 #define UINTMAX_C(c) c ## UL
|
