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    Searched refs:UvdBootLevel (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smumgr.h 50 UvdBootLevel,
smu7_fusion.h 242 uint8_t UvdBootLevel;
smu7_discrete.h 339 uint8_t UvdBootLevel;
smu72_discrete.h 281 uint8_t UvdBootLevel;
smu73_discrete.h 265 uint8_t UvdBootLevel;
smu74_discrete.h 299 uint8_t UvdBootLevel;
smu75_discrete.h 305 uint8_t UvdBootLevel;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 242 uint8_t UvdBootLevel;
smu7_discrete.h 338 uint8_t UvdBootLevel;
radeon_ci_dpm.c 3628 table->UvdBootLevel = 0;
4091 pi->smc_state_table.UvdBootLevel = 0;
4093 pi->smc_state_table.UvdBootLevel =
4098 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
cikd.h 53 # define UvdBootLevel(x) ((x) << 24)
radeon_kv_dpm.c 1451 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1572 table->UvdBootLevel = 0;
2331 case UvdBootLevel:
2332 return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
2377 smu_data->smc_state_table.UvdBootLevel = 0;
2379 smu_data->smc_state_table.UvdBootLevel =
2382 UvdBootLevel);
2388 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2398 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
amdgpu_vegam_smumgr.c 343 smu_data->smc_state_table.UvdBootLevel = 0;
345 smu_data->smc_state_table.UvdBootLevel =
348 UvdBootLevel);
354 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
364 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
1323 table->UvdBootLevel = 0;
2188 case UvdBootLevel:
2189 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
amdgpu_polaris10_smumgr.c 1411 table->UvdBootLevel = 0;
2189 smu_data->smc_state_table.UvdBootLevel = 0;
2191 smu_data->smc_state_table.UvdBootLevel =
2194 UvdBootLevel);
2200 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2210 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2349 case UvdBootLevel:
2350 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
amdgpu_tonga_smumgr.c 1326 table->UvdBootLevel = 0;
2642 case UvdBootLevel:
2643 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2688 smu_data->smc_state_table.UvdBootLevel = 0;
2690 smu_data->smc_state_table.UvdBootLevel =
2693 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2699 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2710 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
amdgpu_ci_smumgr.c 2015 table->UvdBootLevel = 0;
2874 smu_data->smc_state_table.UvdBootLevel = 0;
2876 smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1;
2879 UvdBootLevel, smu_data->smc_state_table.UvdBootLevel);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 1520 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),

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