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    Searched refs:UvdLevel (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1575 table->UvdLevel[count].MinVoltage = 0;
1576 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1577 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1578 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1580 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1582 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1586 table->UvdLevel[count].VclkFrequency, &dividers);
1590 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1593 table->UvdLevel[count].DclkFrequency, &dividers);
1597 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider
    [all...]
amdgpu_vegam_smumgr.c 1326 table->UvdLevel[count].MinVoltage = 0;
1327 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1328 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1329 table->UvdLevel[count].MinVoltage |=
1340 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1341 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1345 table->UvdLevel[count].VclkFrequency, &dividers);
1349 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1352 table->UvdLevel[count].DclkFrequency, &dividers);
1356 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider
    [all...]
amdgpu_polaris10_smumgr.c 1414 table->UvdLevel[count].MinVoltage = 0;
1415 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1416 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1417 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1428 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1429 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1433 table->UvdLevel[count].VclkFrequency, &dividers);
1437 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1440 table->UvdLevel[count].DclkFrequency, &dividers);
1444 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider
    [all...]
amdgpu_tonga_smumgr.c 1329 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1330 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1331 table->UvdLevel[count].MinVoltage.Vddc =
1334 table->UvdLevel[count].MinVoltage.VddGfx =
1338 table->UvdLevel[count].MinVoltage.Vddci =
1341 table->UvdLevel[count].MinVoltage.Phases = 1;
1346 table->UvdLevel[count].VclkFrequency,
1353 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1356 table->UvdLevel[count].DclkFrequency, &dividers);
1361 table->UvdLevel[count].DclkDivider
    [all...]
amdgpu_ci_smumgr.c 1533 table->UvdLevel[count].VclkFrequency =
1535 table->UvdLevel[count].DclkFrequency =
1537 table->UvdLevel[count].MinVddc =
1539 table->UvdLevel[count].MinVddcPhases = 1;
1542 table->UvdLevel[count].VclkFrequency, &dividers);
1546 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1549 table->UvdLevel[count].DclkFrequency, &dividers);
1553 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1554 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1555 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7_fusion.h 237 SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
smu7_discrete.h 330 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
smu72_discrete.h 272 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
smu73_discrete.h 256 SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD];
smu74_discrete.h 288 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
smu75_discrete.h 294 SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 237 SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
smu7_discrete.h 329 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
radeon_ci_dpm.c 2665 table->UvdLevel[count].VclkFrequency =
2667 table->UvdLevel[count].DclkFrequency =
2669 table->UvdLevel[count].MinVddc =
2671 table->UvdLevel[count].MinVddcPhases = 1;
2675 table->UvdLevel[count].VclkFrequency, false, &dividers);
2679 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2683 table->UvdLevel[count].DclkFrequency, false, &dividers);
2687 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2689 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency)
    [all...]
radeon_kv_dpm.c 885 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 968 offsetof(SMU7_Fusion_DpmTable, UvdLevel),

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