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    Searched refs:VceBootLevel (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smumgr.h 51 VceBootLevel,
smu7_fusion.h 243 uint8_t VceBootLevel;
smu7_discrete.h 340 uint8_t VceBootLevel;
smu72_discrete.h 282 uint8_t VceBootLevel;
smu73_discrete.h 266 uint8_t VceBootLevel;
smu74_discrete.h 300 uint8_t VceBootLevel;
smu75_discrete.h 306 uint8_t VceBootLevel;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 243 uint8_t VceBootLevel;
smu7_discrete.h 339 uint8_t VceBootLevel;
cikd.h 50 # define VceBootLevel(x) ((x) << 16)
radeon_ci_dpm.c 3629 table->VceBootLevel = 0;
4133 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4136 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
radeon_kv_dpm.c 1499 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1437 table->VceBootLevel = 0;
2333 case VceBootLevel:
2334 return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2411 smu_data->smc_state_table.VceBootLevel =
2414 smu_data->smc_state_table.VceBootLevel = 0;
2417 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2423 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2430 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
amdgpu_vegam_smumgr.c 377 smu_data->smc_state_table.VceBootLevel =
380 smu_data->smc_state_table.VceBootLevel = 0;
383 offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
389 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
396 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
1210 table->VceBootLevel = 0;
2190 case VceBootLevel:
2191 return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
amdgpu_polaris10_smumgr.c 1305 table->VceBootLevel = 0;
2223 smu_data->smc_state_table.VceBootLevel =
2226 smu_data->smc_state_table.VceBootLevel = 0;
2229 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2235 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2242 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2351 case VceBootLevel:
2352 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
amdgpu_tonga_smumgr.c 1386 table->VceBootLevel = 0;
2644 case VceBootLevel:
2645 return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2723 smu_data->smc_state_table.VceBootLevel =
2727 offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2733 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2741 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
amdgpu_ci_smumgr.c 1572 table->VceBootLevel = 0;
2016 table->VceBootLevel = 0;
2910 VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 1565 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),

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