HomeSort by: relevance | last modified time | path
    Searched refs:VceLevel (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7_fusion.h 238 SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
smu7_discrete.h 331 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
smu72_discrete.h 273 SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
smu73_discrete.h 257 SMU73_Discrete_ExtClkLevel VceLevel [SMU73_MAX_LEVELS_VCE];
smu74_discrete.h 289 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
smu75_discrete.h 295 SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 238 SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
smu7_discrete.h 330 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
radeon_ci_dpm.c 2708 table->VceLevel[count].Frequency =
2710 table->VceLevel[count].MinVoltage =
2712 table->VceLevel[count].MinPhases = 1;
2716 table->VceLevel[count].Frequency, false, &dividers);
2720 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2722 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2723 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
radeon_kv_dpm.c 949 offsetof(SMU7_Fusion_DpmTable, VceLevel),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1440 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1441 table->VceLevel[count].MinVoltage = 0;
1442 table->VceLevel[count].MinVoltage |=
1444 table->VceLevel[count].MinVoltage |=
1447 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1451 table->VceLevel[count].Frequency, &dividers);
1456 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1458 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1459 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
amdgpu_vegam_smumgr.c 1213 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1214 table->VceLevel[count].MinVoltage = 0;
1215 table->VceLevel[count].MinVoltage |=
1227 table->VceLevel[count].MinVoltage |=
1229 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1233 table->VceLevel[count].Frequency, &dividers);
1238 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1240 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1241 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
amdgpu_polaris10_smumgr.c 1308 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1309 table->VceLevel[count].MinVoltage = 0;
1310 table->VceLevel[count].MinVoltage |=
1322 table->VceLevel[count].MinVoltage |=
1324 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1328 table->VceLevel[count].Frequency, &dividers);
1333 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1335 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1336 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
amdgpu_tonga_smumgr.c 1389 table->VceLevel[count].Frequency =
1391 table->VceLevel[count].MinVoltage.Vddc =
1394 table->VceLevel[count].MinVoltage.VddGfx =
1398 table->VceLevel[count].MinVoltage.Vddci =
1401 table->VceLevel[count].MinVoltage.Phases = 1;
1405 table->VceLevel[count].Frequency, &dividers);
1410 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1412 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
amdgpu_ci_smumgr.c 1575 table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
1576 table->VceLevel[count].MinVoltage =
1578 table->VceLevel[count].MinPhases = 1;
1581 table->VceLevel[count].Frequency, &dividers);
1586 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1588 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1589 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 1032 offsetof(SMU7_Fusion_DpmTable, VceLevel),

Completed in 41 milliseconds