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    Searched refs:Voltage (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu12_driver_if.h 49 uint16_t Vid; // min voltage in SVI2 VID
180 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
smu71_discrete.h 40 uint16_t Voltage;
250 // SMIO masks for voltage and phase controls
smu73.h 623 // Voltage Regulator Configuration
706 uint16_t Voltage;
smu7_discrete.h 96 uint16_t Voltage;
smu72_discrete.h 36 uint16_t Voltage;
226 /* SMIO masks for voltage and phase controls */
700 /*Voltage domains */
smu73_discrete.h 34 uint16_t Voltage;
220 // SMIO masks for voltage and phase controls
732 //Voltage domains
smu74.h 695 /* Voltage Regulator Configuration
778 uint16_t Voltage;
smu74_discrete.h 56 uint16_t Voltage;
smu75.h 669 uint16_t Voltage;
smu75_discrete.h 54 uint16_t Voltage;
hwmgr.h 132 uint32_t Voltage;
  /src/sys/external/bsd/gnu-efi/dist/inc/
libsmbios.h 123 UINT8 Voltage;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_discrete.h 96 uint16_t Voltage;
radeon_ci_dpm.c 2217 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2314 SMU7_Discrete_VoltageLevel *voltage)
2322 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2439 u32 clock, u32 *voltage)
2448 *voltage = allowed_clock_voltage_table->entries[i].v;
2453 *voltage = allowed_clock_voltage_table->entries[i-1].v;
3071 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
5045 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 463 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
465 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
491 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
606 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
612 *voltage = *mvdd = 0;
614 /* clock - voltage dependency table is empty table */
621 *voltage |= (dep_table->entries[i].vddc *
624 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
627 *voltage |= (dep_table->entries[i].vddci *
633 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT
    [all...]
amdgpu_iceland_smumgr.c 517 /* clock - voltage dependency table is empty table */
555 * Since voltage in the sclk/vddc dependency table is not
556 * necessarily in ascending order because of ELB voltage
557 * patching, loop through entire list to find exact voltage.
575 * If voltage is not found in the first pass, loop again to
615 smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
634 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
636 /* GPIO voltage control */
661 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
686 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL)
    [all...]
amdgpu_polaris10_smumgr.c 86 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
87 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
359 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
365 *voltage = *mvdd = 0;
367 /* clock - voltage dependency table is empty table */
374 *voltage |= (dep_table->entries[i].vddc *
377 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
380 *voltage |= (dep_table->entries[i].vddci *
386 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
396 *voltage |= 1 << PHASES_SHIFT
    [all...]
amdgpu_tonga_smumgr.c 88 /* [FF, SS] type, [] 4 voltage ranges,
253 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
260 /* clock - voltage dependency table is empty table */
267 voltage->VddGfx = phm_get_voltage_index(
270 voltage->Vddc = phm_get_voltage_index(
275 voltage->Vddci =
278 voltage->Vddci =
286 voltage->Phases = 1;
292 voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
294 voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table
    [all...]
amdgpu_fiji_smumgr.c 71 /* [FF, SS] type, [] 4 voltage ranges, and
92 /* Min Sclk pcie DeepSleep Activity CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display Enabled Enabled Voltage Power */
93 /* Voltage, Frequency, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
361 uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
366 *voltage = *mvdd = 0;
369 /* clock - voltage dependency table is empty table */
376 *voltage |= (dep_table->entries[i].vddc *
379 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
382 *voltage |= (dep_table->entries[i].vddci *
388 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT
    [all...]
amdgpu_ci_smumgr.c 837 smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
856 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
858 /* GPIO voltage control */
886 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
914 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
937 "can not populate VDDC voltage table to SMC", return -EINVAL);
941 "can not populate VDDCI voltage table to SMC", return -EINVAL);
945 "can not populate MVDD voltage table to SMC", return -EINVAL);
961 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
969 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage *
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_processpptables.c 1537 table->entries[i].Voltage = (unsigned long)le16_to_cpu(ptable->entries[i].usVoltage);
amdgpu_smu7_hwmgr.c 182 * Enable voltage control
203 * Checks if we want to support voltage control
216 * Enable voltage control
223 /* enable voltage control */
237 "Voltage Dependency Table empty.", return -EINVAL;);
254 * Create Voltage Tables.
307 /* VDDGFX has only SVI2 voltage control */
337 "Too many voltage values for VDDC. Trimming to fit state table.",
344 "Too many voltage values for VDDC. Trimming to fit state table.",
351 "Too many voltage values for VDDCI. Trimming to fit state table."
    [all...]

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