| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd_v1_0.c | 232 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
282 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
285 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
286 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
296 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
326 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
328 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
347 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
349 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
360 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1))
[all...] |
| radeon_rs780_dpm.c | 207 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
210 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
219 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
222 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
225 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
266 WREG32_P(FVTHROT_PWM_CTRL_REG0,
270 WREG32_P(FVTHROT_PWM_CTRL_REG0,
274 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
278 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
280 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM)
[all...] |
| radeon_vce_v1_0.c | 227 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
228 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
229 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
232 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
235 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
257 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
300 WREG32_P(VCE_STATUS, 1, ~1);
316 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
318 WREG32_P(VCE_SOFT_RESET,
326 WREG32_P(VCE_SOFT_RESET, 0, ~
[all...] |
| radeon_vce_v2_0.c | 167 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
168 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
169 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
173 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
195 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
197 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
|
| radeon_r600_dpm.c | 252 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
254 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
274 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
276 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
282 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
284 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
289 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
295 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
297 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
311 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF)
[all...] |
| radeon_r600_hdmi.c | 191 WREG32_P(acr_ctl + offset,
197 WREG32_P(HDMI0_ACR_32_0 + offset,
200 WREG32_P(HDMI0_ACR_32_1 + offset,
204 WREG32_P(HDMI0_ACR_44_0 + offset,
207 WREG32_P(HDMI0_ACR_44_1 + offset,
211 WREG32_P(HDMI0_ACR_48_0 + offset,
214 WREG32_P(HDMI0_ACR_48_1 + offset,
315 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
361 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
375 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset
[all...] |
| radeon_dce3_1_afmt.c | 185 WREG32_P(HDMI0_ACR_32_0 + offset,
188 WREG32_P(HDMI0_ACR_32_1 + offset,
192 WREG32_P(HDMI0_ACR_44_0 + offset,
195 WREG32_P(HDMI0_ACR_44_1 + offset,
199 WREG32_P(HDMI0_ACR_48_0 + offset,
202 WREG32_P(HDMI0_ACR_48_1 + offset,
|
| radeon_sumo_dpm.c | 96 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
98 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
99 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
100 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
133 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
180 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
186 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
282 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
284 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
441 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK)
[all...] |
| radeon_rv770_dpm.c | 138 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
140 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
141 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
142 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
181 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
186 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
188 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
190 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
202 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
204 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF)
[all...] |
| radeon_rv6xx_dpm.c | 322 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
329 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
337 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
340 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
347 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
353 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
360 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
362 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
369 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
371 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN)
[all...] |
| radeon_cypress_dpm.c | 98 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
100 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
109 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
110 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
111 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
116 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
147 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
149 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
152 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON)
[all...] |
| radeon_ci_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
235 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
245 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
|
| radeon_si_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
271 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
281 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
|
| radeon_rv730_dpm.c | 457 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
459 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
461 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
473 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
475 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
477 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
|
| radeon_legacy_crtc.c | 336 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
338 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
340 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
352 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
354 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
356 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
953 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
974 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vce_v2_0.c | 135 WREG32_P(mmVCE_SOFT_RESET,
139 WREG32_P(mmVCE_SOFT_RESET, 0,
177 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
178 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
179 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
183 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
205 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
241 WREG32_P(mmVCE_STATUS, 1, ~1);
270 WREG32_P(mmVCE_STATUS, 0, ~1);
296 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8))
[all...] |
| amdgpu_uvd_v4_2.c | 270 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
276 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
283 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
311 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
313 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
315 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
317 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
334 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
348 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1))
[all...] |
| amdgpu_uvd_v5_0.c | 306 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
315 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
318 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
330 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
360 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
379 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
382 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
392 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
395 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
426 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK)
[all...] |
| amdgpu_vce_v4_0.c | 146 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
150 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
372 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
375 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
377 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
384 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
398 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
401 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
614 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));
615 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000)
[all...] |
| amdgpu_si_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
234 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
244 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
|
| amdgpu_jpeg_v2_5.c | 319 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
332 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
336 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
372 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
379 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
|
| amdgpu_vcn_v2_5.c | 763 WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 1,
907 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
925 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
929 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
980 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
984 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
987 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
1007 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
1011 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
1024 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN)
[all...] |
| amdgpu_vce_v3_0.c | 311 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
348 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
533 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
534 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
535 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
539 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
576 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
716 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
| amdgpu_vcn_v1_0.c | 804 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
853 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
857 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
879 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
894 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
937 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1095 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET)
[all...] |
| amdgpu_vcn_v2_0.c | 899 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
903 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
943 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
947 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
977 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
981 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1065 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1108 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0
[all...] |
