| /src/sys/arch/riscv/starfive/ |
| jh71x0_clkc.h | 111 #define JH71X0CLKC_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
112 [_id] = { \
137 #define JH71X0CLKC_GATE(_id, _name, _pname) \
138 [_id] = { \
144 .jcc_reg = (_id) * sizeof(uint32_t), \
171 #define JH71X0CLKC_DIV_FLAGS(_id, _name, _maxdiv, _parent, _flags) \
172 [_id] = { \
177 .jcc_reg = (_id) * sizeof(uint32_t), \
186 #define JH71X0CLKC_DIV(_id, _n, _m, _p) \
187 JH71X0CLKC_DIV_FLAGS((_id), (_n), (_m), (_p), 0
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx_ccm.h | 61 #define IMX_EXTCLK(_id, _name) \
63 .id = (_id), \
87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \
91 .id = (_id), \
102 #define IMX_ROOT_GATE(_id, _name, _pname, _reg) \
103 IMX_ROOT_GATE_INDEX(_id, 0, _name, _pname, _reg)
104 #define IMX_ROOT_GATE_INDEX(_id, _regidx, _name, _pname, _reg) \
105 IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, __BITS(1,0)
[all...] |
| imx7d_ccm.c | 101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
105 #define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \
106 IMX_PLL_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _div_mask, _flags)
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 111 #define RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, _flags) \
113 .id = (_id), \
131 #define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
132 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, 0)
134 #define RK3288_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
135 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3288)
137 #define RK3588_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
138 RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3588)
190 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \
192 .id = (_id), \
[all...] |
| rk3399_pmucru.c | 267 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
269 .id = (_id), \
|
| rk3399_cru.c | 340 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
342 .id = (_id), \
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 48 #define MESON_CLK_RESET(_id, _reg, _bit) \
49 [_id] = { \
79 #define MESON_CLK_FIXED(_id, _name, _rate) \
80 [_id] = { \
105 #define MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, _flags) \
106 [_id] = { \
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \
119 MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, 0)
142 #define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \
143 [_id] = {
[all...] |
| meson8b_pinctrl.c | 162 #define CBUS_GPIO(_id, _gpiobase, _gpiobit, _pullbase, _pullbit) \
163 [_id] = { \
164 .id = (_id), \
165 .name = __STRING(_id), \
278 #define AO_GPIO(_id, _bit) \
279 [_id] = { \
280 .id = (_id), \
281 .name = __STRING(_id), \
|
| mesongxbb_pinctrl.c | 201 #define CBUS_GPIO(_id, _off, _bit) \
202 [_id] = { \
203 .id = (_id), \
204 .name = __STRING(_id), \
362 #define AO_GPIO(_id, _bit) \
363 [_id] = { \
364 .id = (_id), \
365 .name = __STRING(_id), \
|
| mesongxl_pinctrl.c | 177 #define CBUS_GPIO(_id, _off, _bit) \
178 [_id] = { \
179 .id = (_id), \
180 .name = __STRING(_id), \
282 #define AO_GPIO(_id, _bit) \
283 [_id] = { \
284 .id = (_id), \
285 .name = __STRING(_id), \
|
| mesong12a_pinctrl.c | 155 #define CBUS_GPIO(_id, _off, _bit) \
156 [_id] = { \
157 .id = (_id), \
158 .name = __STRING(_id), \
285 #define AO_GPIO(_id, _off, _bit) \
286 [_id] = { \
287 .id = (_id), \
288 .name = __STRING(_id), \
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \
48 [_id] = { \
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \
82 [_id] = { \
129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
131 [_id] = { \
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \
152 SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
182 #define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \
184 [_id] = {
[all...] |
| /src/sys/arch/hpc/stand/hpcboot/menu/ |
| tabwindow.h | 40 int _id; member in class:TabWindowBase
50 _id = id;
78 int _id; member in class:TabWindow
86 _id = id;
|
| tabwindow.cpp | 49 reinterpret_cast <HMENU>(_id), aux->hInstance,
160 item.iImage =(int)_id;
163 _base.insert(_id, item);
|
| /src/sys/external/isc/atheros_hal/ic/ |
| ah_osdep.h | 135 #define OS_MARK(_ah, _id, _v)
|
| /src/include/arpa/ |
| nameser.h | 134 uint16_t _id, _flags, _counts[ns_s_max]; member in struct:__ns_msg
158 #define ns_msg_id(handle) ((handle)._id + 0)
|
| /src/lib/libc/nameser/ |
| ns_parse.c | 121 NS_GET16(handle->_id, msg);
|
| /src/sys/dev/ic/ |
| athvar.h | 424 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
425 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
|
| /src/sys/dev/pci/ |
| if_iwmreg.h | 2362 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
|
