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    Searched refs:_reg_read_2 (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/arch/hpc/stand/hpcboot/sh3/dev/
sh4_dev.cpp 105 r = _reg_read_2(SH4_ICR);
119 DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));
133 if (_reg_read_2(HD64465_SDIDR) != 0x8122) {
139 bitdisp(_reg_read_2(HD64465_SMSCR));
141 bitdisp(_reg_read_2(HD64465_SPCCR));
144 bitdisp(_reg_read_2(HD64465_NIRR));
146 bitdisp(_reg_read_2(HD64465_NIMR));
148 bitdisp(_reg_read_2(HD64465_NITR));
153 bitdisp(_reg_read_2(HD64465_NIRR));
170 _reg_write_2(a, ~_reg_read_2(a) & 0xffff)
    [all...]
sh3_dev.cpp 107 DPRINTF((TEXT("ICR0 0x%08x\n"), _reg_read_2(SH3_ICR0)));
108 DPRINTF((TEXT("ICR1 0x%08x\n"), _reg_read_2(SH3_ICR1)));
109 DPRINTF((TEXT("ICR2 0x%08x\n"), _reg_read_2(SH3_ICR2)));
110 DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER)));
111 DPRINTF((TEXT("IPRA 0x%08x\n"), _reg_read_2(SH3_IPRA)));
112 DPRINTF((TEXT("IPRB 0x%08x\n"), _reg_read_2(SH3_IPRB)));
113 DPRINTF((TEXT("IPRC 0x%08x\n"), _reg_read_2(SH3_IPRC)));
114 DPRINTF((TEXT("IPRD 0x%08x\n"), _reg_read_2(SH3_IPRD)));
115 DPRINTF((TEXT("IPRE 0x%08x\n"), _reg_read_2(SH3_IPRE)));
134 bitdisp(_reg_read_2(SH3_PINTER))
    [all...]
sh_dev.h 94 return (uint32_t)_reg_read_2(va);
sh_dev.cpp 129 r16 = _reg_read_2(SH3_SCSSR2);
167 (_reg_read_2(tab->reg) >> tab->shift) & SH_IPR_MASK));
sh.h 337 while ((_reg_read_2(SH3_SCSSR2) & SCSSR2_TDFE) == 0)
  /src/sys/arch/evbsh3/t_sh7706lan/
t_sh7706lan.c 50 reg = _reg_read_2(SH7709_SCPCR);
58 reg = _reg_read_2(SH3_BCR2);
scimci.c 115 _r = _reg_read_2((reg)); \
132 _r = _reg_read_2((reg)); \
ssumci.c 117 _r = _reg_read_2((reg)); \
134 _r = _reg_read_2((reg)); \
  /src/sys/arch/evbsh3/ap_ms104_sh4/
ap_ms104_sh4.c 105 reg = _reg_read_2(SH4_GPIOIC);
127 reg = _reg_read_2(SH4_GPIOIC);
156 r = _reg_read_2(SH4_GPIOIC);
rs5c316_mainbus.c 119 reg = _reg_read_2(SH4_PDTRA);
134 reg = _reg_read_2(SH4_PDTRA);
163 bit = (_reg_read_2(SH4_PDTRA) & (1 << GPIO_PIN_RTC_SIO)) ? 1 : 0;
177 reg = _reg_read_2(SH4_PDTRA);
shpcmcia.c 347 reg = _reg_read_2(SH4_PDTRA);
529 reg = _reg_read_2(SH4_PDTRA);
560 reg = _reg_read_2(SH4_PDTRA);
813 reg = _reg_read_2(SH4_PDTRA);
822 reg = _reg_read_2(SH4_PDTRA);
827 reg = _reg_read_2(SH4_PDTRA);
842 reg = _reg_read_2(SH4_PDTRA);
847 reg = _reg_read_2(SH4_PDTRA);
852 reg = _reg_read_2(SH4_PDTRA);
  /src/sys/arch/playstation2/ee/
eevar.h 42 #define _reg_read_2(a) __read_2(a) macro
  /src/sys/arch/playstation2/dev/
sbus.c 254 if (_reg_read_2(SBUS_PCMCIA_CSC1_REG16) & 0x080)
275 u_int16_t r = _reg_read_2(SBUS_PCMCIA_TIMR_REG16);
305 u_int16_t r = _reg_read_2(SBUS_PCMCIA3_TIMR_REG16);
spd.c 108 _reg_write_2(SPD_INTR_CLEAR_REG16, _reg_read_2(SPD_INTR_STATUS_REG16));
137 r = _reg_read_2(SPD_INTR_STATUS_REG16);
151 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
if_smap.c 173 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
273 cause = _reg_read_2(SPD_INTR_STATUS_REG16) &
274 _reg_read_2(SPD_INTR_ENABLE_REG16);
278 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
397 r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
528 r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
569 r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
wdc_spd.c 236 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
246 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
emac3.c 81 return (_reg_read_2(a_) << 16) | _reg_read_2(a_ + 2);
  /src/sys/arch/hpcsh/dev/
pfckbd.c 305 dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HP_PDCR_MASK;
306 ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HP_PECR_MASK;
402 cc = _reg_read_2(SH7709_PCCR) & ~PFCKBD_HITACHI_PCCR_MASK;
403 dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HITACHI_PDCR_MASK;
404 ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HITACHI_PECR_MASK;
453 cc = _reg_read_2(SH7709_PCCR) & ~PFCKBD_HITACHI_PCCR_MASK;
454 dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HITACHI_PDCR_MASK;
455 ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HITACHI_PECR_MASK;
  /src/sys/arch/sh3/include/
devreg.h 39 #define _reg_read_2(a) (*(volatile uint16_t *)((vaddr_t)(a))) macro
  /src/sys/arch/hpc/stand/hpcboot/
hpcboot.h 125 #define _reg_read_2(a) (*(volatile uint16_t *)(a)) macro
  /src/sys/arch/hpcsh/dev/hd64465/
hd64465.c 191 dbg_bit_print_msg(_reg_read_2(SH4_ICR), "SH4_ICR");
  /src/sys/arch/sh3/sh3/
interrupt.c 354 r = _reg_read_2(iprreg);
  /src/sys/arch/sh3/dev/
rtc.c 170 year = _reg_read_2(SH4_RYRCNT) & 0x00ff;
shpcic.c 118 if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)
161 _reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
168 _reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
  /src/sys/arch/hpcsh/hpcsh/
machdep.c 606 r = _reg_read_2(HD6446X_NIRR);

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