| /src/sys/arch/playstation2/ee/ |
| timer.c | 69 _reg_write_4(T0_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
70 _reg_write_4(T1_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
71 _reg_write_4(T2_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
72 _reg_write_4(T3_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
80 _reg_write_4(T0_COUNT_REG, 0);
81 _reg_write_4(T0_COMP_REG, 5760);
82 _reg_write_4(T0_MODE_REG, T_MODE_CLKS_BUSCLK256 | T_MODE_ZRET |
91 _reg_write_4(T_COUNT_REG(timer), 0);
92 _reg_write_4(T_COMP_REG(timer), 1);
93 _reg_write_4(T_MODE_REG(timer), T_MODE_CUE | T_MODE_CMPE)
[all...] |
| dmac.c | 88 _reg_write_4(D_ENABLEW_REG, D_ENABLE_SUSPEND);
98 _reg_write_4(D_STAT_REG, D_STAT_SIM);
100 _reg_write_4(D_STAT_REG, D_STAT_MEIM);
103 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK);
106 _reg_write_4(D_ENABLEW_REG, 0);
107 _reg_write_4(D_CTRL_REG, D_CTRL_DMAE);
132 _reg_write_4(D_STAT_REG, dispatch);
167 _reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask);
175 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch));
186 _reg_write_4(D_STAT_REG, ((cur_mask ^ ~mask) | (cur_mask & mask))
[all...] |
| intc.c | 78 _reg_write_4(I_STAT_REG, _reg_read_4(I_STAT_REG));
103 _reg_write_4(I_STAT_REG, dispatch);
136 _reg_write_4(I_MASK_REG, (_reg_read_4(I_MASK_REG) & mask) ^ mask);
144 _reg_write_4(I_MASK_REG, _reg_read_4(I_MASK_REG) & (1 << ch));
154 _reg_write_4(I_MASK_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) &
|
| eevar.h | 48 #define _reg_write_4(a, v) __write_4(a, v) macro
|
| gsfb.c | 360 _reg_write_4(D2_QWC_REG, 0);
361 _reg_write_4(D2_MADR_REG, 0);
362 _reg_write_4(D2_TADR_REG, 0);
363 _reg_write_4(D2_CHCR_REG, 0);
623 _reg_write_4(D2_MADR_REG, addr);
625 _reg_write_4(D2_QWC_REG, bytetoqwc(size));
|
| gs.c | 163 _reg_write_4(GIF_CTRL_REG, 1);
|
| /src/sys/arch/sh3/sh3/ |
| mmu_sh4.c | 55 _reg_write_4(SH4_MMUCR, 0); /* zero wired entry */
68 _reg_write_4(SH4_MMUCR, cr);
82 _reg_write_4(SH4_UTLB_AA | SH4_UTLB_A, va);
101 _reg_write_4(SH4_PTEH, asid); /* set ASID for associative write */
104 _reg_write_4(SH4_PTEH, opteh); /* restore ASID */
118 _reg_write_4(addr, 0);
125 _reg_write_4(addr, 0);
155 _reg_write_4(SH4_UTLB_AA | (e << SH4_UTLB_E_SHIFT), 0);
156 _reg_write_4(SH4_UTLB_DA1 | (e << SH4_UTLB_E_SHIFT), 0);
160 _reg_write_4(SH4_ITLB_AA | (e << SH4_ITLB_E_SHIFT), 0)
[all...] |
| mmu_sh3.c | 53 _reg_write_4(SH3_MMUCR, SH3_MMUCR_TF | SH3_MMUCR_AT);
69 _reg_write_4(SH3_MMUAA | a, 0);
70 _reg_write_4(SH3_MMUDA | a, 0);
89 _reg_write_4(aa, 0);
115 _reg_write_4(aa, 0);
194 _reg_write_4(SH3_MMUAA | a, newa);
195 _reg_write_4(SH3_MMUDA | a, newd);
|
| clock.c | 104 _reg_write_4(SH_(TCNT ## x), 0xffffffff); \
255 _reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
256 _reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
268 _reg_write_4(SH_(TCOR1), 0xffffffff);
274 _reg_write_4(SH_(TCOR2), 0xffffffff);
|
| interrupt.c | 92 _reg_write_4(SH4_INTPRI00, 0);
93 _reg_write_4(SH4_INTMSK00, INTMSK00_MASK_ALL);
460 _reg_write_4(iprreg, r);
509 _reg_write_4(iprreg, bit);
558 _reg_write_4(iprreg, bit);
|
| mmu.c | 111 _reg_write_4(SH_(PTEH), asid);
|
| cache_sh4.c | 137 _reg_write_4(SH4_CCR, SH4_CCR_ICI|SH4_CCR_OCI);
138 _reg_write_4(SH4_CCR, r);
264 _reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
|
| sh3_machdep.c | 201 _reg_write_4(SH3_BRCR, (UBC_CTL_A_AFTER_INSN
205 _reg_write_4(SH3_BAMRA, 0x00000000);
558 _reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
|
| /src/sys/arch/mmeye/stand/boot/ |
| wdvar.h | 74 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
78 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
82 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
86 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
90 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
94 _reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
|
| /src/sys/arch/sh3/dev/ |
| shpcic.c | 141 _reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
144 _reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
146 _reg_write_4(SH4_PCICR, PCICR_BASE);
149 _reg_write_4(SH4_PCICONF2,
154 _reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
156 _reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
159 _reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
161 _reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
166 _reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
168 _reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3))
[all...] |
| /src/sys/arch/evbsh3/ap_ms104_sh4/ |
| ap_ms104_sh4.c | 65 _reg_write_4(SH4_PCTRA, 0);
67 _reg_write_4(SH4_PCTRB, 0);
84 _reg_write_4(SH4_PCTRA, reg);
|
| rs5c316_mainbus.c | 102 _reg_write_4(SH4_PCTRA, reg);
153 _reg_write_4(SH4_PCTRA, reg);
|
| /src/sys/arch/playstation2/dev/ |
| sbus.c | 169 _reg_write_4(SBUS_SMFLG_REG, SMFLG_PCMCIA_INT);
170 _reg_write_4(SBUS_SMFLG_REG, SMFLG_USB_INT);
226 _reg_write_4(SBUS_SMFLG_REG, SMFLG_PCMCIA_INT);
231 _reg_write_4(SBUS_SMFLG_REG, SMFLG_USB_INT);
|
| /src/sys/arch/landisk/stand/boot/ |
| delay.c | 100 _reg_write_4(TCOR, 0xffffffff);
101 _reg_write_4(TCNT, 0xffffffff);
|
| /src/sys/arch/landisk/landisk/ |
| machdep.c | 395 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
412 _reg_write_4(SH4_BCR4, BSC_BCR4_VAL);
422 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
433 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
436 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
446 _reg_write_4(SH4_MCR, BSC_MCR_VAL);
|
| /src/sys/arch/evbsh3/evbsh3/ |
| machdep.c | 368 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
388 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
403 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
407 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
420 _reg_write_4(SH4_MCR, BSC_MCR_VAL);
482 _reg_write_4(SH_(CCR), 0x1);
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/cpu/ |
| sh3.h | 103 #define SH3_MMU_DISABLE() _reg_write_4(SH3_MMUCR, SH3_MMUCR_TF)
|
| /src/sys/arch/sh3/include/ |
| devreg.h | 45 #define _reg_write_4(a, v) \ macro
|
| /src/sys/arch/mmeye/mmeye/ |
| machdep.c | 456 _reg_write_4(SH4_BCR1, 0x0008000d);
458 _reg_write_4(SH4_WCR1, 0x11111111);
459 _reg_write_4(SH4_WCR2, 0xdd7845a7);
460 _reg_write_4(SH4_WCR3, 0x05555555);
461 _reg_write_4(SH4_MCR, 0x500921f4);
507 _reg_write_4(SH3_CCR, SH3_CCR_CE);
516 _reg_write_4(SH3_CCR, SH3_CCR_CE);
517 _reg_write_4(SH3_CCR, SH3_CCR_CF | SH3_CCR_CE); /* cache clear */
518 _reg_write_4(SH3_CCR, SH3_CCR_CE);
|
| /src/sys/arch/hpc/stand/hpcboot/ |
| hpcboot.h | 129 #define _reg_write_4(a, v) (*(volatile uint32_t *)(a) = (v)) macro
|
