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    Searched refs:bank (Results 1 - 25 of 228) sorted by relevancy

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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/gpio/
uniphier-gpio.h 15 #define UNIPHIER_GPIO_PORT(bank, line) \
16 ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
  /src/sys/arch/mips/cavium/
octeon_intr.c 261 int bank; local in function:octeon_intr_init
285 for (bank = 0; bank < NBANKS; bank++) {
289 bank,
290 cpu->cpu_ip2_enable[bank],
291 cpu->cpu_ip3_enable[bank],
292 cpu->cpu_ip4_enable[bank]);
296 for (bank = 0; bank < NBANKS; bank++)
370 const int bank = irq \/ 64; local in function:octeon_intr_establish
433 const int bank = irq \/ 64; local in function:octeon_intr_disestablish
482 int bank; local in function:octeon_iointr
    [all...]
  /src/sys/arch/arm/samsung/
exynos_gpio.c 241 #define GPIO_WRITE(bank, reg, val) \
242 bus_space_write_4((bank)->bank_sc->sc_bst, \
243 (bank)->bank_sc->sc_bsh, \
244 (bank)->bank_core_offset + (reg), (val))
245 #define GPIO_READ(bank, reg) \
246 bus_space_read_4((bank)->bank_sc->sc_bst, \
247 (bank)->bank_sc->sc_bsh, \
248 (bank)->bank_core_offset + (reg))
254 struct exynos_gpio_bank *bank = gba->gba_gc->gp_cookie; local in function:exynos_gpio_cfprint
255 const char *bankname = bank->bank_name
268 struct exynos_gpio_bank * const bank = cookie; local in function:exynos_gpio_pin_read
281 struct exynos_gpio_bank * const bank = cookie; local in function:exynos_gpio_pin_write
297 struct exynos_gpio_bank * const bank = cookie; local in function:exynos_gpio_pin_ctl
375 struct exynos_gpio_bank *bank = local in function:exynos_gpio_bank_config
423 struct exynos_gpio_bank *bank; local in function:exynos_gpio_bank_lookup
456 struct exynos_gpio_bank *bank = NULL; local in function:exynos_gpio_fdt_acquire
    [all...]
exynos_pinctrl.c 166 struct exynos_gpio_bank *bank; local in function:exynos_do_config
177 bank = exynos_gpio_bank_lookup(epb, pins);
179 if (bank == NULL) {
184 exynos_gpio_pin_ctl_write(bank, gc, pin);
  /src/sys/arch/arm/nvidia/
tegra_gpio.c 139 #define GPIO_WRITE(bank, reg, val) \
140 bus_space_write_4((bank)->bank_sc->sc_bst, \
141 (bank)->bank_sc->sc_bsh, \
142 (bank)->bank_pb->base + (reg), (val))
143 #define GPIO_READ(bank, reg) \
144 bus_space_read_4((bank)->bank_sc->sc_bst, \
145 (bank)->bank_sc->sc_bsh, \
146 (bank)->bank_pb->base + (reg))
202 struct tegra_gpio_bank *bank = &sc->sc_banks[bankno]; local in function:tegra_gpio_attach_bank
206 bank->bank_sc = sc
240 struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie; local in function:tegra_gpio_cfprint
254 struct tegra_gpio_bank *bank = priv; local in function:tegra_gpio_pin_read
264 struct tegra_gpio_bank *bank = priv; local in function:tegra_gpio_pin_write
275 struct tegra_gpio_bank *bank = priv; local in function:tegra_gpio_pin_ctl
298 const u_int bank = be32toh(gpio[1]) >> 3; local in function:tegra_gpio_fdt_acquire
389 struct tegra_gpio_bank bank; local in function:tegra_gpio_acquire
    [all...]
  /src/sys/dev/ic/
mcp23xxxgpioreg.h 61 * of IOCON.BANK:
63 * IOCON.BANK=1 IOCON.BANK=0 Register
88 * The MCP23x08, of course, only has a single bank of 8 GPIOs, and it
89 * has an addressing schme that operates like IOCON.BANK=1
103 /* IOCON.BANK=1 */
104 #define REGADDR_BANK1(bank, reg) (((bank) << 4) | (reg))
106 /* IOCON.BANK=0 */
107 #define REGADDR_BANK0(bank, reg) (((reg) << 1) | (bank)
    [all...]
nslm7x.c 123 .bank = 0,
131 .bank = 0,
139 .bank = 0,
147 .bank = 0,
155 .bank = 0,
163 .bank = 0,
171 .bank = 0,
181 .bank = 0,
191 .bank = 0,
199 .bank = 0
2751 uint8_t banksel, bank; local in function:wb_refresh_sensor_data
    [all...]
mcp23xxxgpio.c 65 mcpgpio_regaddr(struct mcpgpio_softc *sc, uint8_t bank, uint8_t reg)
72 return REGADDR_BANK1(bank & 1, reg);
74 return REGADDR_BANK0(bank & 1, reg);
98 mcpgpio_bankname(struct mcpgpio_softc *sc, uint8_t bank)
105 return banknames[bank & 1];
132 uint8_t bank, uint8_t reg, uint8_t *valp)
135 uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);
137 error = sc->sc_accessops->read(sc, bank, regaddr, valp);
141 mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),
152 uint8_t bank, uint8_t reg, uint8_t val
182 const uint8_t bank = PIN_BANK(pin); local in function:mcpgpio_gpio_pin_read
209 const uint8_t bank = PIN_BANK(pin); local in function:mcpgpio_gpio_pin_write
239 const uint8_t bank = PIN_BANK(pin); local in function:mcpgpio_gpio_pin_ctl
    [all...]
  /src/sys/arch/arm/rockchip/
rk3399_iomux.c 212 rk3399_iomux_set_bias(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, int flags)
218 KASSERT(bank < sc->sc_conf->nbanks);
220 struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
221 if (RK3399_IOMUX_BANK_IS_PMU(bank)) {
222 reg = 0x00040 + (0x10 * bank);
224 reg = 0x0e040 + (0x10 * (bank - 2));
228 const int pull_type = banks[bank].iomux[idx / 8].pull_type;
248 printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));
266 rk3399_iomux_set_drive_strength(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, u_int val
424 const u_int bank = be32toh(pins[0]); local in function:rk3399_iomux_pinctrl_set_config
    [all...]
rk3328_iomux.c 145 rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)
149 KASSERT(bank < sc->sc_conf->nbanks);
151 *reg = banks[bank].iomux[pin / 8].base;
152 if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
164 rk3328_iomux_set_bias(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int bias)
166 WR4(sc, GRF_GPIO_P_REG(bank, idx),
172 rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int drv)
174 WR4(sc, GRF_GPIO_E_REG(bank, idx),
180 rk3328_iomux_set_mux(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
185 rk3328_iomux_calc_iomux_reg(sc, bank, idx, &reg, &mask)
256 const u_int bank = be32toh(pins[0]); local in function:rk3328_iomux_pinctrl_set_config
    [all...]
rk3288_iomux.c 126 rk3288_iomux_get_reg(struct rk3288_iomux_softc *sc, u_int bank, u_int idx,
129 if (bank >= NBANKS || idx >= NPINSPERBANK) {
133 if (bank == 0) {
141 reg->pull_reg = 0x130 + (bank * 0x10) + (idx / 8) * 4;
143 reg->drv_reg = 0x1b0 + (bank * 0x10) + (idx / 8) * 4;
146 reg->flags = rk3288_iomux_flags[bank][idx / 8];
147 reg->mux_reg = rk3288_iomux_offset[bank][idx / 8];
294 const u_int bank = be32toh(pins[0]); local in function:rk3288_iomux_pinctrl_set_config
300 if (rk3288_iomux_get_reg(sc, bank, idx, &regdef)) {
302 printf(" -> gpio%u P%c%u (%u)\n", bank, 'A' + (idx / 8), idx % 8, idx)
    [all...]
  /src/sys/dev/spi/
mcp23xxxgpio_spi.c 138 mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank,
144 KASSERT(bank < (sc->sc_npins >> 3));
146 buf[0] = OP_READ(ssc->sc_ha[bank]);
153 mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank,
159 KASSERT(bank < (sc->sc_npins >> 3));
161 buf[0] = OP_WRITE(ssc->sc_ha[bank]);
241 int bank, nchips, error, ha; local in function:mcpgpio_spi_attach
266 * XXX Going on blind faith that IOCON.BANK is already 0.
321 /* Record the hardware addresses for each logical bank of 8 pins. */
322 for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha))
    [all...]
  /src/sys/arch/arm/broadcom/
bcm2835_gpio.c 267 int bank; local in function:bcmgpio_attach
332 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) {
335 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) {
342 bank);
343 sc->sc_banks[bank].sc_bankno = bank;
344 sc->sc_banks[bank].sc_bcm = sc;
345 sc->sc_banks[bank].sc_ih = fdtbus_intr_establish_xname(phandle
534 int bank = eint->eint_bank; local in function:bcmgpio_intr_disable
587 const u_int bank = be32toh(specifier[0]) \/ 32; local in function:bcmgpio_fdt_intr_establish
631 int bank = pin \/ 32; local in function:bcmgpio_gpio_intr_establish
697 const u_int bank = be32toh(specifier[0]) \/ 32; local in function:bcmgpio_fdt_intrstr
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_gt_irq.c 46 const unsigned int bank, const unsigned int bit)
53 raw_reg_write(gt->uncore, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
61 ident = raw_reg_read(gt->uncore, GEN11_INTR_IDENTITY_REG(bank));
67 bank, bit, ident);
71 raw_reg_write(gt->uncore, GEN11_INTR_IDENTITY_REG(bank),
130 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
137 intr_dw = raw_reg_read(gt->uncore, GEN11_GT_INTR_DW(bank));
140 const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
146 raw_reg_write(gt->uncore, GEN11_GT_INTR_DW(bank), intr_dw);
151 unsigned int bank; local in function:gen11_gt_irq_handler
    [all...]
intel_gt_irq.h 29 const unsigned int bank,
  /src/sys/arch/amiga/dev/
gtscreg.h 56 vu_short bank; member in struct:sdmac
  /src/sys/dev/i2c/
mcp23xxxgpio_i2c.c 105 mcpgpio_i2c_read(struct mcpgpio_softc *sc, unsigned int bank,
111 KASSERT((bank & ~1U) == 0);
118 mcpgpio_i2c_write(struct mcpgpio_softc *sc, unsigned int bank,
124 KASSERT((bank & ~1U) == 0);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
stm32f7-pinctrl.dtsi 27 st,bank-name = "GPIOA";
37 st,bank-name = "GPIOB";
47 st,bank-name = "GPIOC";
57 st,bank-name = "GPIOD";
67 st,bank-name = "GPIOE";
77 st,bank-name = "GPIOF";
87 st,bank-name = "GPIOG";
97 st,bank-name = "GPIOH";
107 st,bank-name = "GPIOI";
117 st,bank-name = "GPIOJ"
    [all...]
stm32f4-pinctrl.dtsi 63 st,bank-name = "GPIOA";
73 st,bank-name = "GPIOB";
83 st,bank-name = "GPIOC";
93 st,bank-name = "GPIOD";
103 st,bank-name = "GPIOE";
113 st,bank-name = "GPIOF";
123 st,bank-name = "GPIOG";
133 st,bank-name = "GPIOH";
143 st,bank-name = "GPIOI";
153 st,bank-name = "GPIOJ"
    [all...]
  /src/games/trek/
phaser.c 62 ** direction you want each bank to be aimed, the number
108 struct banks bank[NBANKS]; local in function:phaser
154 /* initialize the bank[] array */
157 bank[i].units = 0;
165 b = &bank[i];
218 b = &bank[i];
249 b = &bank[i];
270 b = &bank[i];
283 b = &bank[i];
287 printf("\nPhaser bank %d fires:\n", i)
    [all...]
  /src/sys/arch/powerpc/isa/
isadma_machdep.c 166 int error, cookieflags, bank; local in function:_isa_bus_dmamap_create
171 for (bank = uvm_physseg_get_first();
172 uvm_physseg_valid_p(bank);
173 bank = uvm_physseg_get_next(bank)) {
174 if (avail_end < uvm_physseg_get_avail_end(bank) << PGSHIFT)
175 avail_end = uvm_physseg_get_avail_end(bank) << PGSHIFT;
601 int bank; local in function:_isa_bus_dmamem_alloc
603 for (bank = uvm_physseg_get_first();
604 uvm_physseg_valid_p(bank);
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/pic32/
pic32mzda.dtsi 96 microchip,gpio-bank = <0>;
110 microchip,gpio-bank = <1>;
124 microchip,gpio-bank = <2>;
138 microchip,gpio-bank = <3>;
152 microchip,gpio-bank = <4>;
166 microchip,gpio-bank = <5>;
180 microchip,gpio-bank = <6>;
194 microchip,gpio-bank = <7>;
210 microchip,gpio-bank = <8>;
224 microchip,gpio-bank = <9>
    [all...]
  /src/sys/dev/pci/qat/
qat_c2xxx.c 148 qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank)
151 * For now, all rings within the bank are setup such that the generation
156 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL,
158 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2,
  /src/sys/arch/arm/amlogic/
meson_pinctrl.h 64 u_int bank[MESON_PINCTRL_MAXBANK]; member in struct:meson_pinctrl_group
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_ras_eeprom.h 75 unsigned char bank; member in union:eeprom_table_record::__anon76fad6fc020a

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