| /src/sys/external/bsd/drm/dist/shared-core/ |
| savage_state.c | 797 const struct drm_clip_rect *boxes)
827 x = boxes[i].x1, y = boxes[i].y1;
828 w = boxes[i].x2 - boxes[i].x1;
829 h = boxes[i].y2 - boxes[i].y1;
867 unsigned int nbox, const struct drm_clip_rect *boxes)
885 DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1))
[all...] |
| r128_state.c | 41 struct drm_clip_rect * boxes, int count)
51 OUT_RING(boxes[0].x1);
52 OUT_RING(boxes[0].x2 - 1);
53 OUT_RING(boxes[0].y1);
54 OUT_RING(boxes[0].y2 - 1);
60 OUT_RING(boxes[1].x1);
61 OUT_RING(boxes[1].x2 - 1);
62 OUT_RING(boxes[1].y1);
63 OUT_RING(boxes[1].y2 - 1);
69 OUT_RING(boxes[2].x1)
[all...] |
| radeon_state.c | 753 x += dev_priv->sarea_priv->boxes[0].x1;
754 y += dev_priv->sarea_priv->boxes[0].y1;
803 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
807 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
812 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
817 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
825 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
830 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
861 struct drm_clip_rect *pbox = sarea_priv->boxes;
1229 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i])
2782 struct drm_clip_rect __user *boxes = cmdbuf->boxes; local in function:radeon_emit_packet3_cliprect
[all...] |
| mach64_drm.h | 133 struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; member in struct:drm_mach64_sarea
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| mga_state.c | 508 struct drm_clip_rect *pbox = sarea_priv->boxes;
598 struct drm_clip_rect *pbox = sarea_priv->boxes;
669 &sarea_priv->boxes[i]);
716 &sarea_priv->boxes[i]);
804 struct drm_clip_rect *pbox = sarea_priv->boxes;
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| radeon_drm.h | 440 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; member in struct:__anon601bc9571908
631 struct drm_clip_rect __user *boxes; member in struct:drm_radeon_cmd_buffer
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| i915_dma.c | 392 struct drm_clip_rect __user * boxes,
399 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
489 struct drm_clip_rect __user *boxes = batch->cliprects; local in function:i915_dispatch_batchbuffer
505 int ret = i915_emit_box(dev, boxes, i,
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| mga_drm.h | 184 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; member in struct:_drm_mga_sarea
189 * exported_ fields and puts the cliprects into boxes, above.
192 * clobbering the boxes data.
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| r128_drm.h | 156 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; member in struct:drm_r128_sarea
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| radeon_irq.c | 282 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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| mach64_state.c | 227 struct drm_clip_rect *pbox = sarea_priv->boxes;
366 struct drm_clip_rect *pbox = sarea_priv->boxes;
602 &sarea_priv->boxes[i]);
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| radeon_cp.c | 249 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
279 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
303 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1860 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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| radeon_drv.h | 312 u32 boxes; member in struct:drm_radeon_private::__anon601befa00108
420 struct drm_clip_rect __user *boxes; member in struct:drm_radeon_kcmd_buffer
555 /* Flags for stats.boxes
2027 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2030 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
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| i915_drv.h | 416 struct drm_clip_rect __user *boxes,
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| r600_cp.c | 79 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
104 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2309 struct drm_clip_rect *pbox = sarea_priv->boxes;
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| /src/sys/external/bsd/drm2/dist/drm/savage/ |
| savage_state.c | 811 const struct drm_clip_rect *boxes)
840 x = boxes[i].x1, y = boxes[i].y1;
841 w = boxes[i].x2 - boxes[i].x1;
842 h = boxes[i].y2 - boxes[i].y1;
880 unsigned int nbox, const struct drm_clip_rect *boxes)
898 DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1))
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/r128/ |
| r128_state.c | 52 struct drm_clip_rect *boxes, int count)
62 OUT_RING(boxes[0].x1);
63 OUT_RING(boxes[0].x2 - 1);
64 OUT_RING(boxes[0].y1);
65 OUT_RING(boxes[0].y2 - 1);
71 OUT_RING(boxes[1].x1);
72 OUT_RING(boxes[1].x2 - 1);
73 OUT_RING(boxes[1].y1);
74 OUT_RING(boxes[1].y2 - 1);
80 OUT_RING(boxes[2].x1)
[all...] |
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| i810_drm.h | 165 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; member in struct:_drm_i810_sarea
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| via_drm.h | 190 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; member in struct:_drm_via_sarea
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| mga_drm.h | 192 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; member in struct:_drm_mga_sarea
197 * exported_ fields and puts the cliprects into boxes, above.
200 * clobbering the boxes data.
|
| r128_drm.h | 164 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; member in struct:drm_r128_sarea
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| radeon_drm.h | 449 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; member in struct:__anon05888ab01908
669 struct drm_clip_rect __user *boxes; member in struct:drm_radeon_cmd_buffer
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| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_surface.c | 81 * @boxes: Array of SVGA3dBoxes indicating dirty regions. One per subresource.
87 SVGA3dBox boxes[0]; member in struct:vmw_surface_dirty
1844 SVGA3dBox *box = &dirty->boxes[loc_start->sub_resource];
1892 SVGA3dBox *box = &dirty->boxes[subres];
1951 SVGA3dBox *box = &dirty->boxes[0];
2006 const SVGA3dBox *box = &dirty->boxes[i];
2024 const SVGA3dBox *box = &dirty->boxes[i];
2054 memset(&dirty->boxes[0], 0, sizeof(dirty->boxes[0]) *
2088 dirty_size = sizeof(*dirty) + num_subres * sizeof(dirty->boxes[0])
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/mga/ |
| mga_state.c | 490 struct drm_clip_rect *pbox = sarea_priv->boxes;
578 struct drm_clip_rect *pbox = sarea_priv->boxes;
646 &sarea_priv->boxes[i]);
693 &sarea_priv->boxes[i]);
776 struct drm_clip_rect *pbox = sarea_priv->boxes;
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| /src/sys/external/bsd/drm2/dist/drm/i810/ |
| i810_dma.c | 604 struct drm_clip_rect *pbox = sarea_priv->boxes;
677 struct drm_clip_rect *pbox = sarea_priv->boxes;
724 struct drm_clip_rect *box = sarea_priv->boxes;
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