/src/sys/external/bsd/drm2/include/linux/ |
device.h | 58 #define dev_warn(DEV, FMT, ...) do { \ macro 64 #define dev_WARN dev_warn 92 #define dev_warn_ratelimited dev_warn
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/src/sys/external/bsd/drm2/dist/drm/radeon/ |
radeon_evergreen_cs.c | 224 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 247 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", 255 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", 290 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 297 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", 323 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 342 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 353 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", 363 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", 373 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n" [all...] |
radeon_r600_cs.c | 370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 428 dev_warn(p->dev, "%s offset[%d] 0x%"PRIx64" 0x%"PRIx64", %d not aligned\n", __func__, i, 456 dev_warn(p->dev, "%s offset[%d] %d %"PRIu64" %d %lu too big (%d %d) (%d %d %d)\n", 487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " 505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " 515 dev_warn(p->dev, "%s invalid tile mode\n", __func__) [all...] |
radeon_r520.c | 147 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 236 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 281 dev_warn(rdev->dev,
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radeon_device.c | 493 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 505 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 512 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 598 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 604 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 636 dev_warn(rdev->dev, "limiting GTT\n"); 642 dev_warn(rdev->dev, "limiting GTT\n"); 1230 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1240 dev_warn(rdev->dev, "gart size (%d) too small\n", 1244 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n" [all...] |
radeon_agp.c | 164 dev_warn(rdev->dev, "AGP aperture too small (%zuM) " 282 dev_warn(rdev->dev, "radeon AGP reinit failed\n");
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radeon_rs400.c | 407 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 481 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 554 dev_warn(rdev->dev,
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radeon_r420.c | 326 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 416 dev_warn(rdev->dev,
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radeon_rs600.c | 907 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 1006 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 1089 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1163 dev_warn(rdev->dev,
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/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
amdgpu_common_baco.c | 80 dev_warn(adev->dev, "Invalid BACO command.\n");
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_gfx.c | 322 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 352 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 360 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 386 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 393 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 405 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 412 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 425 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 432 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
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amdgpu_gmc_v6_0.c | 255 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 283 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 444 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 589 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 874 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 1037 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
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amdgpu_amdkfd_arcturus.c | 84 dev_warn(adev->dev,
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amdgpu_cik_ih.c | 205 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_rlc.c | 106 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
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amdgpu_si_ih.c | 119 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_cz_ih.c | 207 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_gmc.c | 216 dev_warn(adev->dev, "limiting GART\n");
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amdgpu_gmc_v7_0.c | 281 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 305 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 565 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 1220 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
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amdgpu_iceland_ih.c | 207 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_tonga_ih.c | 209 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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/src/sys/external/bsd/dwc2/ |
dwc2.h | 79 #define dev_warn(d,fmt,...) do { \ macro 101 #define dev_warn(...) do { } while (0) macro
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/src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/ |
intel_uc_fw.c | 298 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", 311 dev_warn(dev, 324 dev_warn(dev, "%s firmware %s: unexpected key size: %u != %u\n", 335 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", 345 dev_warn(dev, "%s firmware %s: invalid size: %zu > %zu\n",
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/src/sys/external/bsd/dwc2/dist/ |
dwc2_coreintr.c | 115 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 545 dev_warn(hsotg->dev, "Controller is dead\n");
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/src/sys/external/bsd/drm2/dist/drm/qxl/ |
qxl_object.c | 269 dev_warn(ddev->dev, "%p unpin not necessary\n", bo);
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