| /src/sys/dev/fdt/ |
| display_timing.h | 1 /* $NetBSD: display_timing.h,v 1.2 2020/12/11 09:40:28 skrll Exp $ */
32 struct display_timing { struct
45 int display_timing_parse(int, struct display_timing *);
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| panel_fdt.h | 39 #include <dev/fdt/display_timing.h>
61 struct display_timing panel_timing;
|
| display_timing.c | 1 /* $NetBSD: display_timing.c,v 1.1 2017/06/03 14:48:02 jmcneill Exp $ */
30 __KERNEL_RCSID(0, "$NetBSD: display_timing.c,v 1.1 2017/06/03 14:48:02 jmcneill Exp $");
39 #include <dev/fdt/display_timing.h>
45 display_timing_parse(int phandle, struct display_timing *timing)
|
| panel_fdt.c | 91 const struct display_timing * const timing =
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_panel.h | 38 struct display_timing;
127 struct display_timing *timings);
|
| /src/sys/arch/arm/fdt/ |
| plfb_fdt.c | 51 #include <dev/fdt/display_timing.h>
256 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing)
274 struct display_timing timing;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| smu7_hwmgr.h | 292 struct smu7_display_timing display_timing; member in struct:smu7_hwmgr
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| vega10_hwmgr.h | 346 struct vega10_display_timing display_timing; member in struct:vega10_hwmgr
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| vega12_hwmgr.h | 349 struct vega12_display_timing display_timing; member in struct:vega12_hwmgr
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| vega20_hwmgr.h | 473 struct vega20_display_timing display_timing; member in struct:vega20_hwmgr
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| amdgpu_smu7_hwmgr.c | 3629 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3631 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3647 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4181 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4184 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4188 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4189 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
|
| amdgpu_vega12_hwmgr.c | 2443 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2447 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
|
| amdgpu_vega10_hwmgr.c | 3361 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4755 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4759 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
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| amdgpu_vega20_hwmgr.c | 3822 if (data->display_timing.num_existing_displays !=
3827 (data->display_timing.min_clock_in_sr !=
|
| /src/sys/dev/pci/ |
| unichromereg.h | 696 struct display_timing { struct
716 struct display_timing crtc;
|
| unichromefb.c | 167 static void uni_load_crtc(struct unichromefb_softc *, struct display_timing,
746 struct display_timing crtreg;
807 struct display_timing device_timing, int iga)
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 936 data->display_timing.min_clock_in_sr =
943 data->display_timing.min_clock_in_sr);
1287 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1288 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
|
| amdgpu_tonga_smumgr.c | 663 data->display_timing.min_clock_in_sr =
670 data->display_timing.min_clock_in_sr);
1021 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1022 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1028 && (data->display_timing.num_existing_displays <= 2)
1029 && (data->display_timing.num_existing_displays != 0))
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| amdgpu_fiji_smumgr.c | 981 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
1206 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1207 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
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| amdgpu_vegam_smumgr.c | 841 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
1015 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1016 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
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| amdgpu_polaris10_smumgr.c | 949 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
1111 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1112 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
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| amdgpu_ci_smumgr.c | 1239 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1240 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
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