| /src/sys/arch/i386/pci/ |
| piixreg.h | 44 #define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
45 ((1 << (irq)) & PIIX_PIRQ_MASK) != 0)
|
| opti82c558reg.h | 34 * PCI IRQ Select Register
49 #define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
50 ((1 << (irq)) & VIPER_PIRQ_MASK) != 0)
|
| sis85c503reg.h | 51 #define SIS85C503_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
52 ((1 << (irq)) & SIS85C503_PIRQ_MASK) != 0)
|
| opti82c700reg.h | 38 #define FIRESTAR_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
39 ((1 << (irq)) & FIRESTAR_PIRQ_MASK) != 0)
|
| via82c586reg.h | 64 #define VP3_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
65 ((1 << (irq)) & VP3_PIRQ_MASK) != 0)
|
| /src/sys/dev/isa/ |
| wssreg.h | 43 #define WSS_IRQ_VALID(irq) ((irq) == 7 || (irq) == 9 || \
44 (irq) == 10 || (irq) == 11)
|
| /src/sys/external/bsd/drm2/include/linux/ |
| hardirq.h | 40 * synchronize_irq(irq)
42 * Wait for all interrupt handlers servicing irq to complete on
48 synchronize_irq(int irq)
56 synchronize_hardirq(int irq)
|
| /src/sys/arch/ia64/include/ |
| isa_machdep.h | 34 isa_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level,
37 return intr_establish(irq, type, level, ih_func, ih_arg);
41 #define isa_intr_establish_xname(ic, irq, type, level, fun, arg, xname) \
42 isa_intr_establish(ic, irq, type, level, fun, arg)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/interrupt-controller/ |
| mips-gic.h | 7 #include <dt-bindings/interrupt-controller/irq.h>
|
| apple-aic.h | 7 #include <dt-bindings/interrupt-controller/irq.h>
|
| /src/sys/arch/arm/ofw/ |
| ofw_irqhandler.c | 39 * IRQ/FIQ initialisation, claim, release and handler routines
71 * Initialise the IRQ/FIQ sub system
79 /* Clear all the IRQ handlers and the irq block masks */
98 /* Enable IRQ's and FIQ's */
104 * int irq_claim(int irq, irqhandler_t *handler)
106 * Enable an IRQ and install a handler for it.
110 irq_claim(int irq, irqhandler_t *handler, const char *group, const char *name)
123 * IRQ_INSTRUCT indicates that we should get the irq number
124 * from the irq structur
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| interrupt.c | 50 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
51 #define get_irq_info(irq, e) (irq->events[e].info)
53 #define irq_to_gvt(irq) \
54 container_of(irq, struct intel_gvt, irq)
155 struct intel_gvt_irq *irq = &gvt->irq; local in function:regbase_to_irq_info
158 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX)
327 struct intel_gvt_irq *irq = &vgpu->gvt->irq; local in function:update_upstream_irq
471 struct intel_gvt_irq *irq = &vgpu->gvt->irq; local in function:gen8_check_pending_irq
627 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_vgpu_trigger_virtual_event
653 struct intel_gvt_irq *irq; local in function:vblank_timer_fn
675 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_gvt_clean_irq
694 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_gvt_init_irq
[all...] |
| /src/sys/arch/powerpc/pic/ |
| i8259_common.c | 65 i8259_enable_irq(struct pic_ops *pic, int irq, int type)
69 i8259->irqs |= 1 << irq;
79 i8259_disable_irq(struct pic_ops *pic, int irq)
82 uint32_t mask = 1 << irq;
90 i8259_ack_irq(struct pic_ops *pic, int irq)
92 if (irq < 8) {
93 isa_outb(IO_ICU1, 0xe0 | irq);
95 isa_outb(IO_ICU2, 0xe0 | (irq & 7));
103 int irq; local in function:i8259_get_irq
106 irq = isa_inb(IO_ICU1) & 0x07
[all...] |
| pic_openpic.c | 56 int irq; local in function:setup_openpic
97 for (irq = 0; irq < (pic->pic_numintrs - 1); irq++) {
99 openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK);
101 openpic_write(OPENPIC_IDEST(irq), 1 << 0);
116 for (irq = 0; irq < pic->pic_numintrs; irq++) {
121 irq = 0
[all...] |
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_irqhandler.c | 116 int i, irq, ipl; local in function:intr_calculatemasks
120 /* First, figure out which levels each IRQ uses. */
121 for (irq = 0; irq < ICU_LEN; irq++) {
123 for (q = irqhandlers[irq]; q; q = q->ih_next)
125 intrlevel[irq] = ipls;
131 for (irq = 0; irq < ICU_LEN; irq++
232 int irq = ih->ih_irq; local in function:sa11x0_intr_disestablish
266 int irq = (int)p; local in function:stray_irqhandler
281 int irq; local in function:dumpirqhandlers
[all...] |
| /src/sys/arch/evbppc/pmppc/ |
| pic_cpc700.c | 81 cpc700_pic_enable_irq(struct pic_ops *pic, int irq, int type)
83 cpc700_enable_irq(irq);
87 cpc700_pic_disable_irq(struct pic_ops *pic, int irq)
89 cpc700_disable_irq(irq);
95 int irq; local in function:cpc700_get_irq
97 irq = cpc700_read_irq();
98 if (irq < 0)
100 return irq;
104 cpc700_ack_irq(struct pic_ops *pic, int irq)
106 cpc700_eoi(irq);
[all...] |
| /src/sys/arch/rs6000/rs6000/ |
| pic_iocc.c | 87 int irq; local in function:iocc_get_irq
94 irq = 31 - __builtin_clz(rv);
95 if (irq >= 0 && irq < 16)
96 return irq;
100 /* enable an IRQ on the IOCC */
102 iocc_enable_irq(struct pic_ops *pic, int irq, int type)
107 mask |= 1 << irq;
111 /* disable an IRQ on the IOCC */
113 iocc_disable_irq(struct pic_ops *pic, int irq)
[all...] |
| /src/sys/arch/arm/iomd/ |
| iomd_irqhandler.c | 37 * IRQ/FIQ initialisation, claim, release and handler routines
75 * Initialise the IRQ/FIQ sub system
83 /* Clear all the IRQ handlers and the irq block masks */
87 /* Clear the IRQ/FIQ masks in the IOMD */
120 /* Enable IRQ's and FIQ's */
126 * int irq_claim(int irq, irqhandler_t *handler)
128 * Enable an IRQ and install a handler for it.
132 irq_claim(int irq, irqhandler_t *handler)
146 * IRQ_INSTRUCT indicates that we should get the irq numbe
[all...] |
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_intr.c | 120 ixp12x0_enable_irq(int irq)
122 if (irq < SYS_NIRQ) {
123 intr_enabled |= (1U << irq);
124 switch (irq) {
133 panic("enable_irq:bad IRQ %d", irq);
136 pci_intr_enabled |= (1U << (irq - SYS_NIRQ));
137 IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ));
142 ixp12x0_disable_irq(int irq)
144 if (irq < SYS_NIRQ)
172 int irq, ipl; local in function:ixp12x0_intr_calculate_masks
385 int irq; local in function:ixp12x0_intr_dispatch
[all...] |
| /src/sys/arch/arm/xscale/ |
| ixp425_intr.c | 150 ixp425_enable_irq(int irq)
153 intr_enabled |= (1U << irq);
158 ixp425_disable_irq(int irq)
161 intr_enabled &= ~(1U << irq);
166 ixp425_irq2gpio_bit(int irq)
180 if (int2gpio[irq] == 0xff)
181 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq);
183 return (1U << int2gpio[irq]);
194 int irq, ipl local in function:ixp425_intr_calculate_masks
389 int oldirqstate, irq, ibit, hwpend; local in function:ixp425_intr_dispatch
[all...] |
| /src/sys/arch/powerpc/powerpc/ |
| openpic.c | 13 openpic_enable_irq(int irq, int type)
17 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
23 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
27 openpic_disable_irq(int irq)
31 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
33 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
|
| /src/sys/arch/shark/isa/ |
| isa_irqhandler.c | 70 * IRQ/FIQ initialisation, claim, release and handler routines
108 * Initialise the IRQ/FIQ sub system
116 /* Clear all the IRQ handlers and the irq block masks */
135 /* Enable IRQ's and FIQ's */
141 * int irq_claim(int irq, irqhandler_t *handler)
143 * Enable an IRQ and install a handler for it.
147 irq_claim(int irq, irqhandler_t *handler, const char *group, const char *name)
159 * IRQ_INSTRUCT indicates that we should get the irq number
160 * from the irq structur
273 int irq, level; local in function:irq_calculatemasks
[all...] |
| /src/sys/arch/arm/ep93xx/ |
| ep93xx_intr.c | 87 ep93xx_enable_irq(int irq)
89 if (irq < VIC_NIRQ) {
90 vic1_intr_enabled |= (1U << irq);
91 VIC1REG(EP93XX_VIC_IntEnable) = (1U << irq);
93 vic2_intr_enabled |= (1U << (irq - VIC_NIRQ));
94 VIC2REG(EP93XX_VIC_IntEnable) = (1U << (irq - VIC_NIRQ));
99 ep93xx_disable_irq(int irq)
101 if (irq < VIC_NIRQ) {
102 vic1_intr_enabled &= ~(1U << irq);
103 VIC1REG(EP93XX_VIC_IntEnClear) = (1U << irq);
118 int irq, ipl; local in function:ep93xx_intr_calculate_masks
341 int irq; local in function:ep93xx_intr_dispatch
[all...] |
| /src/sys/arch/i386/eisa/ |
| eisa_machdep.c | 131 eisa_intr_map(eisa_chipset_tag_t ec, u_int irq,
134 if (irq >= NUM_LEGACY_IRQS) {
135 aprint_error("eisa_intr_map: bad IRQ %d\n", irq);
139 if (irq == 2) {
140 aprint_verbose("eisa_intr_map: changed IRQ 2 to IRQ 9\n");
141 irq = 9;
146 if (intr_find_mpmapping(mp_eisa_bus, irq, ihp) == 0 ||
147 intr_find_mpmapping(mp_isa_bus, irq, ihp) == 0)
163 int irq; local in function:eisa_intr_string
200 int pin, irq; local in function:eisa_intr_establish
[all...] |
| /src/sys/arch/alpha/pci/ |
| sio_pic.c | 279 specific_eoi(int irq)
281 if (irq > 7) {
283 OCW2_EOI | OCW2_SL | (irq & 0x07)); /* XXX */
286 OCW2_EOI | OCW2_SL | (irq > 7 ? 2 : irq));
290 sio_setirqstat(int irq, int enabled, int type)
296 printf("sio_setirqstat: irq %d: %s, %s\n", irq,
300 icu = irq / 8;
301 bit = irq % 8
502 int ist, irq = ih->ih_num; local in function:sio_intr_disestablish
569 const int irq = __SHIFTOUT(pirqreg, PIRQ_RTCTRL_IRQ); local in function:sio_pirq_intr_map
584 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); local in function:sio_pci_intr_string
592 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); local in function:sio_pci_intr_evcnt
601 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); local in function:sio_pci_intr_establish
621 int bus, irq; local in function:sio_pciide_compat_intr_establish
656 int irq; local in function:sio_iointr
[all...] |
