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    Searched refs:le32_to_cpup (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/common/include/asm/
byteorder.h 63 #define le32_to_cpup le32dec macro
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gmc_v8_0.c 342 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
343 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
347 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
408 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
409 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
417 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
amdgpu_gmc_v6_0.c 200 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
201 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
205 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
amdgpu_gmc_v7_0.c 217 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
218 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
222 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
amdgpu_gfx_v7_0.c 2496 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2506 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2516 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2755 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2777 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
3567 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
amdgpu_gfx_v6_0.c 2001 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2010 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2019 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2561 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
amdgpu_cik_sdma.c 570 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
amdgpu_gfx_v9_0.c 2990 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3088 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3098 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3108 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3295 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
amdgpu_sdma_v5_0.c 817 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
amdgpu_sdma_v4_0.c 1375 le32_to_cpup(fw_data++));
amdgpu_gfx_v10_0.c 1883 le32_to_cpup(fw_data++));
2952 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik_sdma.c 491 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
500 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
radeon_si.c 1645 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1646 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1655 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
3516 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3525 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3534 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
5908 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
radeon_cik.c 1938 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1939 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1957 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
3940 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3949 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3958 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4296 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4310 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
5978 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
  /src/sys/dev/pci/
if_iwm.c 151 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) macro
3371 uint32_t radio_cfg = le32_to_cpup(phy_sku + IWM_RADIO_CFG_8000);
3380 sku = le32_to_cpup(phy_sku + IWM_SKU_8000);
if_iwmreg.h 5155 return le32_to_cpup((uint32_t *)&tx_resp->status +

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