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    Searched refs:mc_reg_address (Results 1 - 23 of 23) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
ci_smumgr.h 60 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:ci_mc_reg_table
iceland_smumgr.h 59 SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:iceland_mc_reg_table
tonga_smumgr.h 61 SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:tonga_mc_reg_table
amdgpu_iceland_smumgr.c 1705 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1707 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2478 table->mc_reg_address[i].s0 =
2479 iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2480 ? address : table->mc_reg_address[i].s1;
2496 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2525 switch (table->mc_reg_address[i].s1) {
2529 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2530 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP
    [all...]
amdgpu_ci_smumgr.c 1738 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1740 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2549 table->mc_reg_address[i].s0 =
2550 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2551 ? address : table->mc_reg_address[i].s1;
2567 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2596 switch (table->mc_reg_address[i].s1) {
2600 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2601 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP
    [all...]
amdgpu_tonga_smumgr.c 2083 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
2085 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2939 table->mc_reg_address[i].s0 =
2940 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
2943 table->mc_reg_address[i].s1;
2959 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2988 switch (table->mc_reg_address[i].s1) {
2993 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2994 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cypress_dpm.c 962 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
964 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
977 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
978 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
981 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
982 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
985 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
986 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
989 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
990 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2
    [all...]
cypress_dpm.h 41 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member in struct:evergreen_mc_reg_table
si_dpm.h 119 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:si_mc_reg_table
ci_dpm.h 89 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:ci_mc_reg_table
ni_dpm.h 59 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:ni_mc_reg_table
radeon_btc_dpm.c 1929 switch (table->mc_reg_address[i].s1) {
1932 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
1933 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1945 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
1946 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1961 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
1962 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1989 table->mc_reg_address[i].s0 =
1990 btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
1991 address : table->mc_reg_address[i].s1
    [all...]
radeon_ni_dpm.c 2721 switch (table->mc_reg_address[i].s1) {
2726 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
2727 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2737 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
2738 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2752 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2753 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2844 table->mc_reg_address[i].s0 =
2845 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
2846 address : table->mc_reg_address[i].s1
    [all...]
radeon_ci_dpm.c 4352 switch(table->mc_reg_address[i].s1 << 2) {
4355 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4356 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4366 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4367 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4379 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4380 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4392 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4393 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4507 table->mc_reg_address[i].s0
    [all...]
radeon_si_dpm.c 5369 switch (table->mc_reg_address[i].s1 << 2) {
5372 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5373 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5383 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5384 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5397 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5398 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5409 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5410 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5504 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
    [all...]
radeon_mode.h 669 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:atom_mc_reg_table
radeon_atombios.c 4019 reg_table->mc_reg_address[i].s1 =
4021 reg_table->mc_reg_address[i].pre_reg_data =
4037 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4041 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios.h 118 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:atom_mc_reg_table
si_dpm.h 281 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member in struct:evergreen_mc_reg_table
627 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:ni_mc_reg_table
935 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:si_mc_reg_table
amdgpu_atombios.c 1613 reg_table->mc_reg_address[i].s1 =
1615 reg_table->mc_reg_address[i].pre_reg_data =
1631 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1635 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
amdgpu_si_dpm.c 5830 switch (table->mc_reg_address[i].s1) {
5833 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5834 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5844 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5845 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5858 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5859 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5868 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5869 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5960 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
ppatomctrl.h 253 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:pp_atomctrl_mc_reg_table
amdgpu_ppatomctrl.c 74 if ((table->mc_reg_address[i].uc_pre_reg_data &
79 } else if ((table->mc_reg_address[i].uc_pre_reg_data &
123 table->mc_reg_address[i].s1 =
125 table->mc_reg_address[i].uc_pre_reg_data =

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