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    Searched refs:mmSRBM_STATUS (Results 1 - 21 of 21) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_ih.c 360 u32 tmp = RREG32(mmSRBM_STATUS);
376 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
389 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_cz_ih.c 339 u32 tmp = RREG32(mmSRBM_STATUS);
355 tmp = RREG32(mmSRBM_STATUS);
367 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_iceland_ih.c 339 u32 tmp = RREG32(mmSRBM_STATUS);
355 tmp = RREG32(mmSRBM_STATUS);
367 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_tonga_ih.c 350 u32 tmp = RREG32(mmSRBM_STATUS);
366 tmp = RREG32(mmSRBM_STATUS);
378 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_uvd_v4_2.c 638 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
647 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
amdgpu_uvd_v5_0.c 561 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
570 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
amdgpu_gmc_v7_0.c 1170 u32 tmp = RREG32(mmSRBM_STATUS);
1187 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1204 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_gmc_v6_0.c 994 u32 tmp = RREG32(mmSRBM_STATUS);
1021 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_gmc_v8_0.c 1298 u32 tmp = RREG32(mmSRBM_STATUS);
1315 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1333 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_uvd_v6_0.c 1122 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1142 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_uvd_v7_0.c 1445 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1465 u32 tmp = RREG32(mmSRBM_STATUS);
amdgpu_vi.c 486 {mmSRBM_STATUS},
amdgpu_cik.c 981 {mmSRBM_STATUS},
amdgpu_si.c 988 {mmSRBM_STATUS},
amdgpu_gfx_v7_0.c 4660 tmp = RREG32(mmSRBM_STATUS);
amdgpu_gfx_v8_0.c 4991 tmp = RREG32(mmSRBM_STATUS);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_1_0_d.h 265 #define mmSRBM_STATUS 0x0394
oss_2_4_d.h 83 #define mmSRBM_STATUS 0x394
oss_2_0_d.h 76 #define mmSRBM_STATUS 0x394
oss_3_0_1_d.h 81 #define mmSRBM_STATUS 0x394
oss_3_0_d.h 93 #define mmSRBM_STATUS 0x394

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