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    Searched refs:of_getprop_uint32 (Results 1 - 25 of 113) sorted by relevancy

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  /src/sys/dev/fdt/
fdt_spi.c 206 if (of_getprop_uint32(node, "spi-max-frequency", &val32) == 0) {
220 if (of_getprop_uint32(node, "spi-cs-setup-delay-ns", &val32) == 0) {
223 if (of_getprop_uint32(node, "spi-cs-hold-delay-ns", &val32) == 0) {
226 if (of_getprop_uint32(node, "spi-cs-inactive-delay-ns", &val32) == 0) {
231 if (of_getprop_uint32(node, "spi-rx-bus-width", &val32) == 0) {
241 if (of_getprop_uint32(node, "spi-rx-delay-us", &val32) == 0) {
249 if (of_getprop_uint32(node, "rx-sample-delay-ns", &val32) == 0) {
254 if (of_getprop_uint32(node, "spi-tx-bus-width", &val32) == 0) {
264 if (of_getprop_uint32(node, "spi-tx-delay-us", &val32) == 0) {
display_timing.c 42 of_getprop_uint32(phandle, (n), (v))
fdt_iommu.c 87 if (of_getprop_uint32(phandle, "#iommu-cells", &cells) != 0) {
130 if (of_getprop_uint32(iommu_phandle, "#iommu-cells", &cells)) {
168 if (of_getprop_uint32(phandle, "iommu-map-mask", &map_mask) == 0) {
183 if (of_getprop_uint32(iommu_phandle, "#iommu-cells", &cells)) {
dw_apb_uart.c 94 if (of_getprop_uint32(phandle, "reg-shift", &reg_shift)) {
98 if (of_getprop_uint32(phandle, "reg-io-width", &reg_iowidth)) {
182 if (of_getprop_uint32(phandle, "reg-shift", &reg_shift)) {
186 if (of_getprop_uint32(phandle, "reg-io-width", &reg_iowidth)) {
fdt_pinctrl.c 104 if (of_getprop_uint32(OF_parent(xref), "#pinctrl-cells", &pinctrl_cells) != 0)
234 if (of_getprop_uint32(phandle, bias_prop, &val) == 0) {
268 if (of_getprop_uint32(phandle, "drive-strength", &val) == 0)
fdt_regulator.c 70 of_getprop_uint32(phandle, "regulator-enable-ramp-delay", &rc->rc_enable_ramp_delay);
184 if (of_getprop_uint32(rc->rc_phandle, "regulator-min-microvolt", &uvol) == 0) {
188 if (of_getprop_uint32(rc->rc_phandle, "regulator-max-microvolt", &uvol) == 0) {
fixedregulator.c 124 if (of_getprop_uint32(phandle, "startup-delay-us", &sc->sc_delay) != 0)
126 of_getprop_uint32(phandle, "regulator-min-microvolt", &sc->sc_min_uvol);
127 of_getprop_uint32(phandle, "regulator-max-microvolt", &sc->sc_max_uvol);
ns8250_uart.c 126 if (of_getprop_uint32(phandle, "reg-shift", &reg_shift)) {
132 if (of_getprop_uint32(phandle, "clock-frequency", &sc->sc_frequency)) {
208 if (of_getprop_uint32(phandle, "reg-shift", &reg_shift)) {
mmc_pwrseq_simple.c 152 of_getprop_uint32(phandle, "post-power-on-delay-ms",
155 of_getprop_uint32(phandle, "power-off-delay-us",
fdt_gpio.c 95 if (of_getprop_uint32(gc_phandle, "#gpio-cells", &gpio_cells))
128 if (of_getprop_uint32(gc_phandle, "#gpio-cells", &gpio_cells))
fixedfactorclock.c 106 of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
107 of_getprop_uint32(phandle, "clock-mult", &sc->sc_clk.mult);
panel_fdt.c 103 if (of_getprop_uint32(phandle, "width-mm", &sc->sc_panel.panel_width) ||
104 of_getprop_uint32(phandle, "height-mm", &sc->sc_panel.panel_height)){
pinctrl_single.c 174 if (of_getprop_uint32(phandle, "pinctrl-single,register-width", &sc->sc_regwidth) != 0) {
178 if (of_getprop_uint32(phandle, "pinctrl-single,function-mask", &sc->sc_funcmask) != 0) {
ahcisata_fdt.c 84 if (of_getprop_uint32(phandle, "ports-implemented", &sc->sc_ahci_ports) != 0)
  /src/sys/arch/riscv/fdt/
cpus_fdt.c 49 int ret = of_getprop_uint32(cpus, "timebase-frequency", &tbfreq);
  /src/sys/arch/arm/nvidia/
tegra_pinmux.c 141 if (of_getprop_uint32(phandle, "nvidia,pull", &val) == 0) {
145 if (of_getprop_uint32(phandle, "nvidia,tristate", &val) == 0) {
149 if (of_getprop_uint32(phandle, "nvidia,open-drain", &val) == 0) {
153 if (of_getprop_uint32(phandle, "nvidia,lock", &val) == 0) {
157 if (of_getprop_uint32(phandle, "nvidia,io-hv", &val) == 0) {
161 if (of_getprop_uint32(phandle, "nvidia,high-speed-mode", &val) == 0) {
165 if (of_getprop_uint32(phandle, "nvidia,schmitt", &val) == 0) {
169 if (of_getprop_uint32(phandle, "nvidia,drive-type", &val) == 0) {
182 if (of_getprop_uint32(phandle, "nvidia,pull-down-strength", &val) == 0) {
186 if (of_getprop_uint32(phandle, "nvidia,pull-up-strength", &val) == 0)
    [all...]
tegra_com.c 100 if (of_getprop_uint32(faa->faa_phandle, "reg-shift", &reg_shift)) {
171 if (of_getprop_uint32(faa->faa_phandle, "reg-shift", &reg_shift)) {
  /src/sys/arch/riscv/starfive/
jh7110_eqos.c 80 if (of_getprop_uint32(phandle,
85 if (of_getprop_uint32(phandle,
90 if (of_getprop_uint32(phandle,
95 if (of_getprop_uint32(phandle,
  /src/sys/arch/arm/samsung/
exynos_pinctrl.c 139 gc->cfg_valid = of_getprop_uint32(phandle, "samsung,pin-function", &gc->cfg) == 0;
140 gc->pud_valid = of_getprop_uint32(phandle, "samsung,pin-pud", &gc->pud) == 0;
141 gc->drv_valid = of_getprop_uint32(phandle, "samsung,pin-drv", &gc->drv) == 0;
142 gc->conpwd_valid = of_getprop_uint32(phandle, "samsung,pin-conpwd", &gc->conpwd) == 0;
143 gc->pudpwd_valid = of_getprop_uint32(phandle, "samsung,pin-pudpwd", &gc->pudpwd) == 0;
  /src/sys/arch/riscv/sifive/
fu540_ccache.c 164 ret = of_getprop_uint32(phandle, "cache-block-size",
171 ret = of_getprop_uint32(phandle, "cache-level",
178 ret = of_getprop_uint32(phandle, "cache-sets",
184 ret = of_getprop_uint32(phandle, "cache-size",
  /src/sys/arch/arm/nxp/
imx_i2c.c 80 error = of_getprop_uint32(phandle, "clock-frequency", &freq);
  /src/sys/dev/ofw/
openfirm.h 137 int of_getprop_uint32(int, const char *, uint32_t *);
  /src/sys/arch/arm/ti/
ti_div_clock.c 170 if (of_getprop_uint32(sc->sc_phandle, "ti,bit-shift", &bit_shift) != 0)
173 if (of_getprop_uint32(sc->sc_phandle, "ti,max-div", &max_div) == 0) {
  /src/sys/arch/arm/fdt/
gtmr_fdt.c 111 if (of_getprop_uint32(phandle, "clock-frequency", &freq) == 0) {
plmmc_fdt.c 98 of_getprop_uint32(phandle, "max-frequency", &sc->sc_max_freq);

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