| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vdsc.h | 22 struct intel_crtc_state *pipe_config);
|
| intel_panel.h | 31 struct intel_crtc_state *pipe_config,
34 struct intel_crtc_state *pipe_config,
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| intel_dvo.c | 168 struct intel_crtc_state *pipe_config)
174 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
186 pipe_config->hw.adjusted_mode.flags |= flags;
188 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
206 const struct intel_crtc_state *pipe_config,
215 &pipe_config->hw.mode,
216 &pipe_config->hw.adjusted_mode);
255 struct intel_crtc_state *pipe_config,
261 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode
[all...] |
| intel_dp_mst.c | 142 struct intel_crtc_state *pipe_config,
154 &pipe_config->hw.adjusted_mode;
162 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
163 pipe_config->has_pch_encoder = false;
166 pipe_config->has_audio =
169 pipe_config->has_audio =
182 limits.min_bpp = intel_dp_min_bpp(pipe_config);
191 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
193 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
195 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
[all...] |
| intel_display.c | 157 struct intel_crtc_state *pipe_config);
159 struct intel_crtc_state *pipe_config);
174 const struct intel_crtc_state *pipe_config);
176 const struct intel_crtc_state *pipe_config);
252 const struct intel_crtc_state *pipe_config)
255 return pipe_config->port_clock; /* SPLL */
1399 const struct intel_crtc_state *pipe_config)
1404 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1413 const struct intel_crtc_state *pipe_config)
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)
8434 struct intel_crtc_state *pipe_config; local in function:vlv_force_pll_on
13978 struct intel_crtc_state *pipe_config = old_crtc_state; local in function:verify_crtc_state
[all...] |
| intel_lvds.c | 125 struct intel_crtc_state *pipe_config)
131 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
143 pipe_config->hw.adjusted_mode.flags |= flags;
146 pipe_config->gmch_pfit.lvds_border_bits =
153 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
156 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
233 const struct intel_crtc_state *pipe_config,
238 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
239 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode
[all...] |
| intel_ddi.c | 1526 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1530 if (pipe_config->has_pch_encoder)
1531 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1532 &pipe_config->fdi_m_n);
1533 else if (intel_crtc_has_dp_encoder(pipe_config))
1534 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1535 &pipe_config->dp_m_n);
1536 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1537 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp
[all...] |
| intel_lspcon.h | 36 const struct intel_crtc_state *pipe_config);
|
| intel_crt.c | 136 struct intel_crtc_state *pipe_config)
138 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
140 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
142 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
146 struct intel_crtc_state *pipe_config)
150 intel_ddi_get_config(encoder, pipe_config);
152 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
156 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
158 pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv)
[all...] |
| intel_hdmi.c | 272 const struct intel_crtc_state *pipe_config)
346 const struct intel_crtc_state *pipe_config)
349 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
426 const struct intel_crtc_state *pipe_config)
429 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
499 const struct intel_crtc_state *pipe_config)
502 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
569 const struct intel_crtc_state *pipe_config)
572 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
1800 struct intel_crtc_state *pipe_config)
[all...] |
| icl_dsi.c | 272 const struct intel_crtc_state *pipe_config)
285 &pipe_config->hw.adjusted_mode;
645 const struct intel_crtc_state *pipe_config)
649 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
665 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
691 if (pipe_config->dsc.compression_enable) {
747 configure_dual_link_mode(encoder, pipe_config);
1082 const struct intel_crtc_state *pipe_config,
1088 gen11_dsi_map_pll(encoder, pipe_config);
1091 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
[all...] |
| intel_pipe_crc.c | 295 struct intel_crtc_state *pipe_config; local in function:intel_crtc_crc_setup_workarounds
311 pipe_config = intel_atomic_get_crtc_state(state, crtc);
312 if (IS_ERR(pipe_config)) {
313 ret = PTR_ERR(pipe_config);
317 pipe_config->uapi.mode_changed = pipe_config->has_psr;
318 pipe_config->crc_enabled = enable;
321 pipe_config->hw.active && crtc->pipe == PIPE_A &&
322 pipe_config->cpu_transcoder == TRANSCODER_EDP)
323 pipe_config->uapi.mode_changed = true
[all...] |
| intel_dp.c | 1793 struct intel_crtc_state *pipe_config)
1815 if (pipe_config->port_clock == divisor[i].clock) {
1816 pipe_config->dpll = divisor[i].dpll;
1817 pipe_config->clock_set = true;
1898 const struct intel_crtc_state *pipe_config)
1906 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1913 const struct intel_crtc_state *pipe_config)
1915 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1932 struct intel_crtc_state *pipe_config)
1938 bpp = pipe_config->pipe_bpp
[all...] |
| vlv_dsi.c | 261 struct intel_crtc_state *pipe_config,
268 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
270 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
274 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
280 intel_gmch_panel_fitting(crtc, pipe_config,
283 intel_pch_panel_fitting(crtc, pipe_config,
294 pipe_config->pipe_bpp = 24;
296 pipe_config->pipe_bpp = 18;
305 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
307 pipe_config->cpu_transcoder = TRANSCODER_DSI_A
[all...] |
| intel_panel.c | 183 struct intel_crtc_state *pipe_config,
186 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
190 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
191 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
192 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
197 width = pipe_config->pipe_src_w;
198 height = pipe_config->pipe_src_h;
207 * pipe_config->pipe_src_h;
208 u32 scaled_height = pipe_config->pipe_src_w
211 width = scaled_height / pipe_config->pipe_src_h
[all...] |
| intel_ddi.h | 39 struct intel_crtc_state *pipe_config);
|
| intel_hdmi.h | 36 struct intel_crtc_state *pipe_config,
|
| intel_dp.h | 40 struct intel_crtc_state *pipe_config,
67 struct intel_crtc_state *pipe_config,
|
| intel_sdvo.c | 1247 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1249 unsigned dotclock = pipe_config->port_clock;
1250 struct dpll *clock = &pipe_config->dpll;
1272 pipe_config->clock_set = true;
1276 struct intel_crtc_state *pipe_config,
1284 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1285 struct drm_display_mode *mode = &pipe_config->hw.mode;
1288 pipe_config->pipe_bpp = 8*3;
1289 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1292 pipe_config->has_pch_encoder = true
[all...] |
| intel_tv.c | 924 const struct intel_crtc_state *pipe_config,
932 to_intel_crtc(pipe_config->uapi.crtc)->pipe);
1089 struct intel_crtc_state *pipe_config)
1093 &pipe_config->hw.adjusted_mode;
1101 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1123 tv_mode.clock = pipe_config->port_clock;
1188 struct intel_crtc_state *pipe_config,
1196 &pipe_config->hw.adjusted_mode;
1206 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1209 pipe_config->pipe_bpp = 8*3
[all...] |
| intel_vdsc.c | 388 struct intel_crtc_state *pipe_config)
390 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
391 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
395 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
396 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
398 pipe_config->dsc.slice_count);
407 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
|
| intel_overlay.c | 937 const struct intel_crtc_state *pipe_config = local in function:check_overlay_dst
940 if (rec->dst_x < pipe_config->pipe_src_w &&
941 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
942 rec->dst_y < pipe_config->pipe_src_h &&
943 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
|
| intel_display.h | 583 struct intel_crtc_state *pipe_config);
598 struct intel_crtc_state *pipe_config);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 159 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
166 plane_state->tiling_info.gfx8.pipe_config,
251 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
255 update->plane_info->tiling_info.gfx8.pipe_config,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 334 unsigned int pipe_config; member in struct:dc_tiling_info::__anon788fbb990708
|
