| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_kv_smc.c | 83 u32 smc_address, u32 limit)
85 if (smc_address & 3)
87 if ((smc_address + 3) > limit)
90 WREG32(mmSMC_IND_INDEX_0, smc_address);
97 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
102 ret = kv_set_smc_sram_address(adev, smc_address, limit);
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| amdgpu_si_smc.c | 39 u32 smc_address, u32 limit)
41 if (smc_address & 3)
43 if ((smc_address + 3) > limit)
46 WREG32(SMC_IND_INDEX_0, smc_address);
250 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
257 ret = si_set_smc_sram_address(adev, smc_address, limit);
265 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
272 ret = si_set_smc_sram_address(adev, smc_address, limit);
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| kv_dpm.h | 223 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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| sislands_smc.h | 419 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
421 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_kv_smc.c | 80 u32 smc_address, u32 limit)
82 if (smc_address & 3)
84 if ((smc_address + 3) > limit)
87 WREG32(SMC_IND_INDEX_0, smc_address);
93 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
98 ret = kv_set_smc_sram_address(rdev, smc_address, limit);
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| radeon_ci_smc.c | 39 u32 smc_address, u32 limit)
41 if (smc_address & 3)
43 if ((smc_address + 3) > limit)
46 WREG32(SMC_IND_INDEX_0, smc_address);
252 u32 smc_address, u32 *value, u32 limit)
258 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
267 u32 smc_address, u32 value, u32 limit)
273 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
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| radeon_si_smc.c | 39 u32 smc_address, u32 limit)
41 if (smc_address & 3)
43 if ((smc_address + 3) > limit)
46 WREG32(SMC_IND_INDEX_0, smc_address);
287 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
294 ret = si_set_smc_sram_address(rdev, smc_address, limit);
302 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
309 ret = si_set_smc_sram_address(rdev, smc_address, limit);
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| rv770_smc.h | 203 u16 smc_address, u32 *value, u16 limit);
205 u16 smc_address, u32 value, u16 limit);
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| ci_dpm.h | 339 u32 smc_address, u32 *value, u32 limit);
341 u32 smc_address, u32 value, u32 limit);
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| radeon_rv770_smc.c | 283 u16 smc_address, u16 limit)
287 if (smc_address & 3)
289 if ((smc_address + 3) > limit)
292 addr = smc_address;
609 u16 smc_address, u32 *value, u16 limit)
615 ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
624 u16 smc_address, u32 value, u16 limit)
630 ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
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| kv_dpm.h | 194 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| sislands_smc.h | 420 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
422 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_smu8_smumgr.c | 117 uint32_t smc_address, uint32_t limit)
122 if (0 != (3 & smc_address)) {
127 if (limit <= (smc_address + 3)) {
133 SMN_MP1_SRAM_START_ADDR + smc_address);
139 uint32_t smc_address, uint32_t value, uint32_t limit)
146 result = smu8_set_smc_sram_address(hwmgr, smc_address, limit);
666 uint32_t smc_address; local in function:smu8_request_smu_load_fw
676 smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
679 smu8_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4)
[all...] |
