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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
hwmgr_ppt.h 39 uint16_t vddc; member in struct:phm_ppt_v1_clock_voltage_dependency_record
68 uint16_t vddc; member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
amdgpu_smu7_hwmgr.c 320 "Failed to retrieve VDDC table.", return result;);
331 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
337 "Too many voltage values for VDDC. Trimming to fit state table.",
344 "Too many voltage values for VDDC. Trimming to fit state table.",
726 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
852 entries[i].vddc = dep_sclk_table->entries[i].vddc;
864 entries[i].vddc = dep_mclk_table->entries[i].vddc;
1706 uint16_t vddc = 0; local in function:smu7_get_evv_voltages
2371 uint32_t vddc, vddci; local in function:smu7_patch_limits_vddc
2391 uint32_t vddc; local in function:smu7_patch_cac_vddc
2516 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; local in function:smu7_get_elb_voltages
    [all...]
amdgpu_vega10_hwmgr.c 347 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
349 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
355 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
357 od_table[2]->entries[i].vddc;
553 * Get Leakage VDDC based on leakage ID.
562 uint32_t vddc = 0; local in function:vega10_get_evv_voltages
587 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
592 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
593 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0)
1873 uint16_t clk = 0, vddc = 0; local in function:vega10_populate_single_display_type
    [all...]
amdgpu_smu_helper.c 40 uint8_t convert_to_vid(uint16_t vddc)
42 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
562 if (req_vddc <= vddc_table->entries[i].vddc) {
563 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
570 " found a available voltage in VDDC DPM Table \n");
697 dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv6xx_dpm.h 42 u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; member in struct:rv6xx_pm_hw_state
84 u16 vddc; member in struct:rv6xx_pl
radeon_btc_dpm.c 1315 u16 *vddc, u16 *vddci)
1320 if ((0 == *vddc) || (0 == *vddci))
1323 if (*vddc > *vddci) {
1324 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1326 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1330 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1333 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
1409 if (ulv_pl->vddc) {
2107 u16 vddc, vddci; local in function:btc_apply_state_adjust_rules
2125 if (ps->high.vddc > max_limits->vddc
    [all...]
radeon_rv6xx_dpm.c 490 pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
491 pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
492 pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
493 pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
513 if ((state->high.vddc == state->medium.vddc) &
1827 u16 vddc; local in function:rv6xx_parse_pplib_clock_info
1869 u16 vddc, vddci, mvdd; local in function:rv6xx_parse_pplib_clock_info
    [all...]
btc_dpm.h 58 u16 *vddc, u16 *vddci);
radeon_rv770_dpm.c 570 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
583 if (vddc <= pi->vddc_table[i].vddc) {
585 voltage->value = cpu_to_be16(vddc);
668 ret = rv770_populate_vddc_value(rdev, pl->vddc,
669 &level->vddc);
947 &table->ACPIState.levels[0].vddc);
961 &table->ACPIState.levels[0].vddc);
1076 initial_state->low.vddc,
1077 &table->initialState.levels[0].vddc);
1697 u16 vddc; local in function:rv770_get_max_vddc
2254 u16 vddc, vddci, mvdd; local in function:rv7xx_parse_pplib_clock_info
    [all...]
rv770_dpm.h 68 u16 vddc; member in struct:vddc_table_entry
84 bool voltage_control; /* vddc */
147 u16 vddc; member in struct:rv7xx_pl
220 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
radeon_ni_dpm.c 751 s64 kt, kv, leakage_w, i_leakage, vddc, temperature; local in function:ni_calculate_leakage_for_v_and_t_formula
754 vddc = div64_s64(drm_int2fixp(v), 1000);
760 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));
762 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
818 if (ps->performance_levels[i].vddc > max_limits->vddc)
819 ps->performance_levels[i].vddc = max_limits->vddc;
842 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
1398 NISLANDS_SMC_VOLTAGE_VALUE vddc; local in function:ni_calculate_power_boost_limit
3972 u16 vddc, vddci, mvdd; local in function:ni_parse_pplib_clock_info
    [all...]
radeon_si_dpm.c 1779 s64 kt, kv, leakage_w, i_leakage, vddc; local in function:si_calculate_leakage_for_v_and_t_formula
1784 vddc = div64_s64(drm_int2fixp(v), 1000);
1793 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1796 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1798 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1817 s64 kt, kv, leakage_w, i_leakage, vddc; local in function:si_calculate_leakage_for_v_formula
1820 vddc = div64_s64(drm_int2fixp(v), 1000);
1824 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1826 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
2299 SISLANDS_SMC_VOLTAGE_VALUE vddc; local in function:si_populate_power_containment_values
2980 u16 vddc, vddci, min_vce_voltage = 0; local in function:si_apply_state_adjust_rules
3240 u16 vddc, count = 0; local in function:si_get_leakage_vddc
6793 u16 vddc, vddci, mvdd; local in function:si_parse_pplib_clock_info
    [all...]
radeon_rv730_dpm.c 251 &table->ACPIState.levels[0].vddc);
258 &table->ACPIState.levels[0].vddc);
369 initial_state->low.vddc,
370 &table->initialState.levels[0].vddc);
rv770_smc.h 112 RV770_SMC_VOLTAGE_VALUE vddc; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
radeon_rv740_dpm.c 339 &table->ACPIState.levels[0].vddc);
347 &table->ACPIState.levels[0].vddc);
nislands_smc.h 112 NISLANDS_SMC_VOLTAGE_VALUE vddc; member in struct:NISLANDS_SMC_HW_PERFORMANCE_LEVEL
radeon_ci_dpm.c 274 static u8 ci_convert_to_vid(u16 vddc)
276 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
301 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
1346 u16 vddc, vddci; local in function:ci_get_leakage_voltages
1355 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1357 if (vddc != 0 && vddc != virtual_voltage_id) {
1358 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1366 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1369 if (vddc != 0 && vddc != virtual_voltage_id)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios.h 177 u16 *vddc, u16 *vddci,
211 u16 *vddc, u16 *vddci, u16 *mvdd);
amdgpu_si_dpm.c 1871 s64 kt, kv, leakage_w, i_leakage, vddc; local in function:si_calculate_leakage_for_v_and_t_formula
1876 vddc = div64_s64(drm_int2fixp(v), 1000);
1885 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1888 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1890 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1909 s64 kt, kv, leakage_w, i_leakage, vddc; local in function:si_calculate_leakage_for_v_formula
1912 vddc = div64_s64(drm_int2fixp(v), 1000);
1916 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1918 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
2397 SISLANDS_SMC_VOLTAGE_VALUE vddc; local in function:si_populate_power_containment_values
3407 u16 vddc; local in function:rv770_get_max_vddc
3440 u16 vddc, vddci, min_vce_voltage = 0; local in function:si_apply_state_adjust_rules
3700 u16 vddc, count = 0; local in function:si_get_leakage_vddc
7195 u16 vddc, vddci, mvdd; local in function:si_parse_pplib_clock_info
    [all...]
amdgpu_dpm.h 116 u16 vddc; member in struct:amdgpu_clock_and_voltage_limits
137 u16 vddc; member in struct:amdgpu_cac_leakage_entry::__anonba5607100108
si_dpm.h 443 RV770_SMC_VOLTAGE_VALUE vddc; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
491 u16 vddc; member in struct:vddc_table_entry
540 bool voltage_control; /* vddc */
603 u16 vddc; member in struct:rv7xx_pl
763 NISLANDS_SMC_VOLTAGE_VALUE vddc; member in struct:NISLANDS_SMC_HW_PERFORMANCE_LEVEL
sislands_smc.h 157 SISLANDS_SMC_VOLTAGE_VALUE vddc; member in struct:SISLANDS_SMC_HW_PERFORMANCE_LEVEL
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
hardwaremanager.h 113 PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
276 uint32_t vddc; member in struct:PHM_PerformanceLevel
388 uint32_t vddc; member in struct:phm_odn_performance_level
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 376 *voltage |= (dep_table->entries[i].vddc *
386 (dep_table->entries[i].vddc -
404 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
411 (dep_table->entries[i].vddc -
773 * We are populating vddc CAC data to BapmVddc table
966 "can not find VDDC voltage value for "
967 "VDDC engine clock dependency table",
1189 "VDDC voltage dependency table", return result);
1329 "Cannot find ACPI VDDC voltage value " \
1443 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT
    [all...]
amdgpu_vegam_smumgr.c 516 * We are populating vddc CAC data to BapmVddc table
621 *voltage |= (dep_table->entries[i].vddc *
631 (dep_table->entries[i].vddc -
649 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
651 (dep_table->entries[i - 1].vddc -
830 "can not find VDDC voltage value for "
831 "VDDC engine clock dependency table",
999 "VDDC voltage dependency table", return result);
1133 "Cannot find ACPI VDDC voltage value "
1216 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT
    [all...]

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