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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vm.c 136 adev->vm_manager.block_size;
161 adev->vm_manager.root_level);
163 if (level == adev->vm_manager.root_level)
165 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
187 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
203 if (level <= adev->vm_manager.root_level)
404 cursor->level = adev->vm_manager.root_level;
754 unsigned level = adev->vm_manager.root_level;
1043 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1082 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]
    [all...]
amdgpu_ids.c 214 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
237 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
238 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
350 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
423 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
485 id_mgr = &adev->vm_manager.id_mgr[vmhub];
512 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
535 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
562 &adev->vm_manager.id_mgr[i];
582 &adev->vm_manager.id_mgr[i]
    [all...]
amdgpu_csa.c 34 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
amdgpu_vm.h 53 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
365 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
366 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
367 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
amdgpu_gfxhub_v1_0.c 107 adev->vm_manager.vram_base_offset;
219 num_level = adev->vm_manager.num_level;
220 block_size = adev->vm_manager.block_size;
257 lower_32_bits(adev->vm_manager.max_pfn - 1));
259 upper_32_bits(adev->vm_manager.max_pfn - 1));
amdgpu_gfxhub_v2_0.c 102 + adev->vm_manager.vram_base_offset;
218 adev->vm_manager.num_level);
235 adev->vm_manager.block_size - 9);
244 lower_32_bits(adev->vm_manager.max_pfn - 1));
246 upper_32_bits(adev->vm_manager.max_pfn - 1));
amdgpu_mmhub_v2_0.c 88 adev->vm_manager.vram_base_offset;
208 adev->vm_manager.num_level);
226 adev->vm_manager.block_size - 9);
235 lower_32_bits(adev->vm_manager.max_pfn - 1));
237 upper_32_bits(adev->vm_manager.max_pfn - 1));
amdgpu_gmc_v6_0.c 465 uint32_t high = adev->vm_manager.max_pfn -
524 field = adev->vm_manager.fragment_size;
548 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
569 ((adev->vm_manager.block_size - 9)
610 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
905 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
913 adev->vm_manager.vram_base_offset = tmp;
915 adev->vm_manager.vram_base_offset = 0;
amdgpu_gmc_v7_0.c 588 uint32_t high = adev->vm_manager.max_pfn -
660 field = adev->vm_manager.fragment_size;
689 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
707 adev->vm_manager.block_size - 9);
1072 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1080 adev->vm_manager.vram_base_offset = tmp;
1082 adev->vm_manager.vram_base_offset = 0;
amdgpu_gmc_v9_0.c 741 *addr = adev->vm_manager.vram_base_offset + *addr -
943 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
946 adev->vm_manager.vram_base_offset +=
1128 adev->vm_manager.num_level > 1;
1230 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1231 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1232 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
amdgpu_mmhub_v1_0.c 123 adev->vm_manager.vram_base_offset;
242 num_level = adev->vm_manager.num_level;
243 block_size = adev->vm_manager.block_size;
280 lower_32_bits(adev->vm_manager.max_pfn - 1));
282 upper_32_bits(adev->vm_manager.max_pfn - 1));
amdgpu_gmc_v10_0.c 573 *addr = adev->vm_manager.vram_base_offset + *addr -
670 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
857 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
858 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
amdgpu_vm_sdma.c 250 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
amdgpu_gmc_v8_0.c 809 uint32_t high = adev->vm_manager.max_pfn -
882 field = adev->vm_manager.fragment_size;
926 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
951 adev->vm_manager.block_size - 9);
1192 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1200 adev->vm_manager.vram_base_offset = tmp;
1202 adev->vm_manager.vram_base_offset = 0;
amdgpu_sdma_v2_4.c 1271 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1273 adev->vm_manager.vm_pte_scheds[i] =
1276 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_si_dma.c 844 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
846 adev->vm_manager.vm_pte_scheds[i] =
849 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_mmhub_v9_4.c 149 adev->vm_manager.vram_base_offset;
319 adev->vm_manager.num_level);
337 adev->vm_manager.block_size - 9);
354 lower_32_bits(adev->vm_manager.max_pfn - 1));
358 upper_32_bits(adev->vm_manager.max_pfn - 1));
amdgpu_cik_sdma.c 1382 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1384 adev->vm_manager.vm_pte_scheds[i] =
1387 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_sdma_v5_0.c 1730 if (adev->vm_manager.vm_pte_funcs == NULL) {
1731 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1733 adev->vm_manager.vm_pte_scheds[i] =
1736 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_sdma_v3_0.c 1709 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1711 adev->vm_manager.vm_pte_scheds[i] =
1714 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_amdkfd.c 123 .gpuvm_size = min(adev->vm_manager.max_pfn
amdgpu_sdma_v4_0.c 2525 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2531 adev->vm_manager.vm_pte_scheds[i] = sched;
2533 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
amdgpu_kms.c 727 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
744 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_vm.c 69 return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
96 if (!rdev->vm_manager.enabled) {
101 rdev->vm_manager.enabled = true;
117 if (!rdev->vm_manager.enabled)
121 radeon_fence_unref(&rdev->vm_manager.active[i]);
123 rdev->vm_manager.enabled = false;
195 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
202 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
203 struct radeon_fence *fence = rdev->vm_manager.active[i];
222 return rdev->vm_manager.active[choices[i]]
    [all...]
radeon_ni.c 1333 rdev->vm_manager.max_pfn - 1);
1335 rdev->vm_manager.saved_table_addr[i]);
1370 rdev->vm_manager.saved_table_addr[i] = RREG32(
2516 rdev->vm_manager.nvm = 8;
2521 rdev->vm_manager.vram_base_offset = tmp;
2523 rdev->vm_manager.vram_base_offset = 0;

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