| /src/sys/arch/vax/boot/xxboot/ |
| start.S | 157 pushr $0x131 # save clobbered registers
171 popr $0x131 # restore clobbered registers
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| ppsmc.h | 122 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 119 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
|
| /src/lib/libform/ |
| form.h | 154 #define REQ_SCR_FCHAR (KEY_MAX + 0x131) /* horizontal scroll
|
| /src/sys/arch/sparc64/sparc64/ |
| hvcall.S | 128 #define RNG_CTL_READ 0x131
|
| locore.s | 821 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
1032 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
|
| /src/sys/dev/i2c/ |
| sht4x.c | 397 crc = (crc << 1) ^ 0x131;
|
| si70xx.c | 463 crc = (crc << 1) ^ 0x131;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 227 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
|
| smu7_ppsmc.h | 224 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
|
| tonga_ppsmc.h | 251 #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 384 #define BTN_EAST 0x131
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| qcom-apq8060-dragonboard.dts | 417 reg = <0x131>;
|
| /src/sys/dev/ic/ |
| rt2860reg.h | 1028 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1206 #define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
|
| gmc_8_1_d.h | 1310 #define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2014 ahd_print_register(NULL, 0, "MSG_OUT", 0x131, regvalue, cur_col, wrap)
3531 #define MSG_OUT 0x131
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_post.c | 1082 param->dram_config = 0x131;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 433 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
1633 SC_PA0_SC_EOPG_WE = 0x131,
|
| gfx_8_1_enum.h | 433 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
1651 SC_PA0_SC_EOPG_WE = 0x131,
|
| gfx_7_2_enum.h | 1448 SC_PA0_SC_EOPG_WE = 0x131,
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1345 x131: sh3add %r26,0,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1 label
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1037 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
|
| dce_10_0_d.h | 1194 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
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| dce_11_0_d.h | 1006 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
|
