| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| ppsmc.h | 125 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
|
| amdgpu_si_dpm.c | 716 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
718 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
781 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
783 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
846 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
848 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
911 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
913 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
976 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
978 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }
[all...] |
| amdgpu_gfx_v9_0.c | 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 122 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
|
| radeon_si_dpm.c | 621 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
623 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
686 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
688 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
751 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
753 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
816 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
818 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
881 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
883 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }
[all...] |
| /src/lib/libform/ |
| form.h | 162 #define REQ_SCR_HFHALF (KEY_MAX + 0x135) /* horizontal scroll
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 231 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
|
| smu7_ppsmc.h | 228 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
|
| tonga_ppsmc.h | 255 #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIDefines.h | 695 DPP_UNUSED5_FIRST = 0x135,
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 392 #define BTN_Z 0x135
|
| /src/external/bsd/openldap/dist/libraries/libldap/ |
| t61.c | 173 0x125, 0xee, 0x135, 0, 0, 0, 0, 0xf4,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1210 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
|
| gmc_8_1_d.h | 1314 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2042 ahd_print_register(NULL, 0, "SAVED_LUN", 0x135, regvalue, cur_col, wrap)
3558 #define SAVED_LUN 0x135
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 437 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
1637 SC_PA1_SC_EVENT_WE = 0x135,
|
| gfx_8_1_enum.h | 437 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
1655 SC_PA1_SC_EVENT_WE = 0x135,
|
| gfx_7_2_enum.h | 1452 SC_PA1_SC_EVENT_WE = 0x135,
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-opc.c | 2204 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-opc.c | 2204 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1353 x135: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1 label
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/pa/ |
| milli64.S | 1964 LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
|
| /src/sys/arch/sparc64/sparc64/ |
| locore.s | 821 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
1032 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1026 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
|
| dce_10_0_d.h | 1183 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
|
