HomeSort by: relevance | last modified time | path
    Searched refs:x154 (Results 1 - 25 of 73) sorted by relevancy

1 2 3

  /src/sys/arch/arm/nvidia/
tegra_xusbreg.h 65 #define XUSB_CSB_FALCON_IMFILLRNG1_REG 0x154
tegra_usbreg.h 32 #define TEGRA_EHCI_TXFILLTUNING_REG 0x154
tegra124_xusbpadreg.h 117 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4_REG 0x154
tegra210_pinmux.c 146 TEGRA_PIN("cam1_mclk_ps0", 0x154, "extperiph3", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/arch/hpcmips/tx/
tx39timerreg.h 40 #define TX39_TIMERPERIODIC_REG 0x154
  /src/sys/arch/mac68k/include/
psc.h 95 #define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm814.h 18 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
dm816.h 18 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mp-evk.dts 328 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
329 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
335 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
336 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
342 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
348 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
  /src/sys/dev/pcmcia/
if_cnwreg.h 89 #define CNW_EREG_SPCQ 0x154
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap4-var-som-om44-wlan.dtsi 41 OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */
  /src/sys/arch/x86/pci/
amdzentemp.c 376 sc->sc_ccd_offset = 0x154;
382 sc->sc_ccd_offset = 0x154;
407 sc->sc_ccd_offset = 0x154;
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 126 #define DBELL_SA_MASK 0x154
  /src/tests/lib/libcurses/tests/
std_defines 67 assign KEY_STAB 0x154
  /src/sys/arch/amiga/amiga/
cc_registers.h 196 #define R_SPR2_DATAA 0x154
  /src/sys/arch/arm/footbridge/
dc21285reg.h 258 #define DOORBELL_SA_MASK 0x154
  /src/sys/arch/arm/s3c2xx0/
s3c2800reg.h 317 #define PCICTL_PCIBAM2 0x154 /* BAR0 mask */
  /src/sys/arch/arm/sunxi/
sun5i_a13_ccu.c 63 #define MALI_CLOCK_CFG_REG 0x154
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 99 #define GPMC_CONFIG2_5 0x154
  /src/sys/dev/pci/
cs4281reg.h 107 #define CS4281_DCR0 0x154 /* DMA Engine 0 Command Register */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 144 #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ppsmc.h 141 #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 218 0x154 MODE_NAND /* qspi_sck */
  /src/lib/libcurses/
keyname.c 199 if (key == 0x154) {
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 274 #define HW_DIGCTL_OCRAM_STATUS4_SET 0x154

Completed in 24 milliseconds

1 2 3